The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 06/08/2022 Version 2022.1 | |
| Power Distribution System | Updated Sysmon power supply (VCCAUX_SMON). |
| PCB Design Considerations | Added XDC constraints description to step 7. |
| Checking for Feedback Structures in Registers | Updated example. |
| Check Inferred Logic | Added information on retiming_forward and retiming_backward. |
| Using the CLOCK_DEDICATED_ROUTE Constraint | Added information on vertically adjacent clock regions. |
| Assessing Post-Synthesis Quality of Results | Updated table. |
| Methodology DRCs with Impact on Timing Closure | Added TIMING-56 check description. |
| Methodology DRCs with Impact on Signoff Quality and Hardware Stability | Added TIMING-54 to 57 check descriptions. |
| Overconstraining the Design | Added overconstrain warning note. |