Xilinx TLM – SystemC Library for ESL Modelling - 2022.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
Document ID
UG1393
Release Date
2022-05-25
Version
2022.1 English

Xilinx TLM (XTLM) is a Xilinx extension of Accellera SystemC TLM 2.0 library for modeling AXI protocols. It provides simulation infrastructure between SystemC to SystemC using custom TLM sockets and also provides the co-simulation infrastructure between RTL and SystemC through Transactors. Though TLM 2.0 consists of sockets, payload, and phases, these default elements are not sufficient to support the full functionality of AXI. Therefore, XTLM has defined its own set of sockets, payload, and phases.

A user of XTLM should be familiar with the basics of SystemC and the TLM 2.0 specifications. The following table provides a brief introduction to classes available inside the XTLM library.

Table 1. XTLM Features and Usage
S. No. XTLM Feature/Classes Usage
1 aximm_payload Transaction object class to describe data over the AXI4 memory map bus in a single transaction.

Based on TLM 2.0 generic payload but not derived from.
2 axis_payload Transaction object class to describe data over the AXI4-Stream bus in a single transaction.

Based on TLM 2.0 generic payload but not derived from it.
3 xtlm_aximm_initiator_socket Basic socket to be used for AXI4 memory map interface in master/initiator.

One socket shall be instantiated for each READ and WRITE socket.
4 xtlm_aximm_simple_initiator_socket_tagged Basic socket to be used for AXI4 memory map interface in master/initiator to bind to multiple interfaces.

One socket shall be instantiated for each READ and WRITE socket.

Each interface has to be added with new ID.
5 xtlm_aximm_target_socket Basic socket to be used for AXI4 memory map interface in slave/target.

One socket shall be instantiated for each READ and WRITE socket.
6 xtlm_aximm_passthrough_target_socket_tagged Basic socket to be used for AXI4 memory map interface in slave/target to bind to multiple interfaces.

One socket shall be instantiated for each READ and WRITE socket.

Each interface has to be added with new ID.
7 xtlm_axis_initiator_socket Basic socket to be used for AXI4-Stream interface in master/initiator.
8 xtlm_axis_simple_initiator_socket_tagged Basic socket to be used for AXI4-Stream interface in master/initiator to bind to multiple interfaces.

Each interface has to be added with new ID.
9 xtlm_axis_target_socket Basic socket to be used for AXI4-Stream interface in slave/target.
10 xtlm_axis_passthrough_target_socket_tagged Basic socket to be used for AXI4-Stream interface in slave/target to bind to multiple interfaces.

Each interface has to be added with new ID.
11 xtlm_aximm_initiator_stub One Initiator socket to stub XTLM slave interface.

This socket is useful where there is no XTLM master.

This avoids port binding errors in SystemC.
12 xtlm_aximm_target_stub One Target socket to stub XTLM master interface.

This socket is useful where there is no XTLM slave.

This avoids port binding errors in SystemC
13 xtlm_axis_initiator_stub One Initiator socket to stub XTLM AXI4-Stream slave interface.

This socket is useful where there is no XTLM AXI4-Stream master.

This avoids port binding errors in SystemC.
14 xtlm_aximm_target_stub One Target socket to stub XTLM master interface.

This socket is useful where there is no XTLM slave.

This avoids port binding errors in SystemC.
15 xtlm_aximm_initiator_rd_socket_util Utility for AXI4 Memory Map Initiator Read Socket.

Works only with xtlm_aximm_initiator_socket type.
16 xtlm_aximm_initiator_wr_socket_util

Utility for AXI4 Memory Map Initiator Write Socket.

Works only with xtlm_aximm_initiator_socket type.
17 xtlm_aximm_target_rd_socket_util Utility for AXI4 Memory Map Target Read Socket.

Works only with xtlm_aximm_target_socket type.
18 xtlm_aximm_target_wr_socket_util Utility for AXI4 Memory Map Target Write Socket.

Works only with xtlm_aximm_target_socket type.