The Vitis tool uses the Vivado logic simulator (xsim
) as the default simulator for all platforms, including Alveo Data Center accelerator cards, and Versal and Zynq UltraScale+ MPSoC embedded platforms. However, for Versal embedded platforms, like xilinx_vck190_base
or custom platforms similar to it, the Vitis tool also supports the use of third-party
simulators for hardware emulation: Mentor Graphics Questa Advanced Simulator, Xcelium,
and VCS. The specific versions of the supported simulators are the same as the versions
supported by Vivado Design Suite.
Enabling a third-party simulator requires some additional configuration
options to be implemented during generation of the device binary (.xclbin) and supporting Tcl scripts. The specific
requirements for each simulator is discussed below. Also, note that you should run the
Vivado setup for third-party simulators before
using those simulators in Vitis. Specifically, you
must pre-compile the simulation models using the compile_sim_lib
Tcl command. For more details, see the
Vivado Design Suite User Guide: Logic
Simulation (UG900) for third-party simulator
setup.
- Questa
- Add the following advanced parameters and Vivado properties to a configuration file for use during linking:
## Final set of additional options required for running simulation using Questa Simulator [advanced] param=hw_emu.simulator=QUESTA [vivado] prop=project.__CURRENT__.simulator.questa_install_dir=/tools/gensys/questa/2020.4/bin/ prop=project.__CURRENT__.compxlib.questa_compiled_library_dir=<install_dir>/clibs/questa/2020.4/lin64/lib/ prop=fileset.sim_1.questa.compile.sccom.cores={4}
After generating the configuration file you can use it in thev++
command line as follows:v++ -link --config questa_sim.cfg
- Xcelium
- Add the following advanced parameters and Vivado properties to a configuration file for use during
linking:
## Final set of additional options required for running simulation using Xcelium Simulator [advanced] param=hw_emu.simulator=XCELIUM [vivado] prop=project.__CURRENT__.simulator.xcelium_install_dir=/tools/dist/xlm/20.09.006/tools.lnx86/xcelium/bin/ prop=project.__CURRENT__.compxlib.xcelium_compiled_library_dir=/clibs/xcelium/20.09.006/lin64/lib/ prop=fileset.sim_1.xcelium.elaborate.xmelab.more_options={-timescale 1ns/1ps}
After generating the configuration file you can use it in thev++
command line as follows:v++ -link --config xcelium.cfg
- VCS
- Add the following advanced parameters and Vivado properties to a configuration file for use during
linking:
## Final set of additional options required for running simulation using VCS Simulator [advanced] param=hw_emu.simulator=VCS [vivado] prop=project.__CURRENT__.simulator.vcs_install_dir=/tools/gensys/vcs/R-2020.12/bin/ prop=project.__CURRENT__.compxlib.vcs_compiled_library_dir=/clibs/vcs/R-2020.12/lin64/lib/ prop=project.__CURRENT__.simulator.vcs_gcc_install_dir=/tools/installs/synopsys/vg_gnu/2019.06/amd64/gcc-6.2.0_64/bin
After generating the configuration file you can use it in thev++
command line as follows:v++ -link --config vcs_sim.cfg
You can use the -user-pre-sim-script
and
-user-post-sim-script
options from the launch_emulator.py
command to specify Tcl scripts to run
before the start of simulation, or after simulation completes. As an example, in these
scripts, you can use the $cwd
command to get the run
directory of the simulator and copy any files needed prior to simulation, or copy any
output files generated at the end of simulation.
To enable hardware emulation, you must set up the environment for simulation
in the Vivado Design Suite. A key step for setup is
pre-compiling the RTL and SystemC models for use with the simulator. To do this, you
must run the compile_sim_lib
command in the Vivado tool. For more information on pre-compilation of
simulation models, refer to the
Vivado Design Suite User Guide: Logic
Simulation (UG900).
When creating your Versal platform ready
for simulation, the Vivado tool generates a
simulation wrapper which must be instantiated in your simulation test bench. So, if the
top most design module is <top>
, then when
calling launch_simulation
in the Vivado tool, it will generate a <top>_sim_wrapper
module, and also generates xlnoc.bd. These files are generated as simulation-only
sources and will be overwritten whenever launch_simulation
is called in the Vivado tool. Platform developers need to instantiate this module in the
test bench and not their own <top>
module.