The RTL kernel wizard automates some of the steps you need to take to ensure that the RTL IP is packaged into a kernel object (XO) file that can be used by the Vitis™ compiler. The RTL Kernel wizard:
- Steps you through the process of specifying the interface requirements for your RTL kernel, and generates a top-level RTL wrapper based on the provided information.
- Automatically generates an AXI4-Lite interface module including the control logic and register file, included in the top level wrapper.
- Includes an example kernel IP module in the top-level wrapper that you can replace with your own RTL IP design, after ensuring correct connectivity between your RTL IP and the wrapper.
- Automatically generates a kernel.xml file to match the kernel specification from the wizard.
- Generates a simple simulation test bench for the generated RTL kernel wrapper.
- Generates an example host program to run and debug the RTL kernel.
The RTL Kernel wizard can be accessed from the Vitis IDE, or from the Vivado® IP catalog. In either case it creates a Vivado project containing an example design to act as a template for defining your own RTL kernel.
The example design consists of a simple RTL IP adder, called VADD, that you can use to
guide you through the process of mapping your own RTL IP into the generated top-level
wrapper. The connections include clock(s), reset(s), s_axilite control
interface, m_axi interfaces, and optionally axis
streaming interfaces.
The Wizard also generates a simple test bench for the generated RTL kernel wrapper, and a sample host code to exercise the example RTL kernel. This example test bench and host code must be modified to test the your RTL IP design accordingly.