OpenCL kernels, C/C++ kernels, and RTL kernels have different methods for assigning function parameters to AXI interfaces.
-
For OpenCL kernels, the
--max_memory_ports
option is required to generate one AXI4 interface for each global pointer on the kernel argument. The AXI4 interface name is based on the order of the global pointers on the argument list.The following code is taken from the example gmem_2banks_ocl in the ocl_kernels category from the Vitis Accel Examples on GitHub:
__kernel __attribute__ ((reqd_work_group_size(1, 1, 1))) void apply_watermark(__global const TYPE * __restrict input, __global TYPE * __restrict output, int width, int height) { ... }
In this example, the first global pointer
input
is assigned an AXI4 nameM_AXI_GMEM0
, and the second global pointeroutput
is assigned a nameM_AXI_GMEM1
. -
For C/C++ kernels, multiple AXI4 interfaces are generated by specifying different “bundle” names in the HLS INTERFACE pragma for different global pointers. Refer to Kernel Interfaces for more information.
The following is a code snippet from the gmem_2banks example that assigns theinput
pointer to the bundlegmem0
and theoutput
pointer to the bundlegmem1
. The bundle name can be any valid C string, and the AXI4 interface name generated will beM_AXI_<bundle_name>
. For this example, the input pointer will have AXI4 interface name asM_AXI_gmem0
, and the output pointer will haveM_AXI_gmem1
. Refer to pragma HLS interface for more information.#pragma HLS INTERFACE m_axi port=input offset=slave bundle=gmem0 #pragma HLS INTERFACE m_axi port=output offset=slave bundle=gmem1
- For RTL kernels, the port names are generated during the import process by
the RTL kernel wizard. The default names proposed by the RTL kernel wizard are
m00_axi
andm01_axi
. If not changed, these names have to be used when assigning a DDR bank through theconnectivity.sp
option in the configuration file. Refer to Mapping Kernel Ports to Memory for more information.