How to Use the create/use xtlm_ipc_verilog_stub Module - 2022.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2022.1 English
  1. Each xtlm_ipc_verilog_stub module must consist of three files:
    • A system verilog wrapper – This module provides a pin-level bus interface for AXIS bus protocol. You must instantiate this module in the User TG top level module, and this bus interface shall be connected to the corresponding SV interface or traffic generator RTL module interface driving the AXIS traffic. This stub SV module is a place holder for the implementation of the SystemC module.
    • A systemC header file (.h) – This file contains the declaration of the systemc module.
    • A systemC implementation file (.cpp) – This systemC module implementation has a transactor which converts the pin level signaling to an axis_payload (tlm payload). This payload is then serialized using Google protobuf and sent via socket communication to the Vitis Emulation/AI Engine simulator/ x86-Simulation process. In the Vitis Emulation/AI Engine simulator/ x86-Simulation process, in the corresponding xtlm_ipc_<master/slave> this payload is de-serialized , converted to pin-level/tlm payload (as per target) driven to the AI Engine/PL kernel.
  2. These modules are ready available as pre-packaged sources with different TDATA_WIDTH configurations here - $XILINX_VIVADO/data/emulation/ip_utils/xtlm_ipc/xtlm_ipc_v1_0/sv available in width configuration of 32, 64, and 128 bits.
    • xtlm_ipc_aie2pl<width>.sv
    • xtlm_ipc_aie2pl<width>.cpp
    • xtlm_ipc_aie2pl<width>.h
    • xtlm_ipc_pl2aie<width>.sv
    • xtlm_ipc_pl2aie<width>.cpp
    • xtlm_ipc_pl2aie<width>.h
  3. You can also create these manually taking hint from the files at above path, if you have need for different configuration.
  4. Two additional files are also required by the xtlm_ipc_verilog_stub module, which are available as sources as part of Vivado installation and need to be compiled.
    • $XILINX_VIVADO/data/emulation/hw_em/ip_repo/sim_ipc_axis_slave_v1_0/sysc/ sim_ipc_axis_slave.cpp
    • $XILINX_VIVADO/data/emulation/hw_em/ip_repo/sim_ipc_axis_master_v1_0/sysc/sim_ipc_axis_master.cpp
    Note: Add the previous directories to include the path during compilation, as they contain additional header files.
  5. The systemC model makes use of various libraries underneath to function. All the libraries binaries and headers are available in Vivado as part of installation.
  6. There are tutorials and example designs available where you can find more details on usage and integration of xtlm_ipc_verilog_stubs in test benches. You can find example compilation, elaboration, and simulation scripts.