XADC Register Interface

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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1.11 English

Chapter 3

XADC Register Interface

Figure 3-1 illustrates the XADC register interface. All registers in the register interface are accessible through the dynamic reconfiguration port (DRP). The DRP can be accessed through a FPGA logic port or the JTAG TAP. Access is governed by an arbitrator (see DRP Arbitration, page 44 ). The DRP allows you to access up to 128 16-bit registers (DADDR[6:0] = 00h to 7Fh ). The first 64 access locations (DADDR[6:0] = 00h to 3Fh ) are read-only and contain the ADC measurement data. These registers are known as status registers. The control registers are located at addresses 40h to 7Fh and are readable or writable through the DRP. The DRP timing is shown in Figure 5-3 .

Figure 3-1: XADC Register Interface

X-Ref Target - Figure 3-1


Notes relevant to Figure 3-1 :

1. Zynq-7000 family of SoC devices only.

For a detailed description of the DRP timing, see Dynamic Reconfiguration Port (DRP) Timing, page 64 . For more information on the JTAG DRP interface, see DRP JTAG Interface, page 40 .