Event-Driven Sampling

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

Document ID
Release Date
1.11 English

Event-Driven Sampling

Figure 5-2 illustrates the event-driven sampling mode. In this operating mode, the sampling instant and subsequent conversion process are initiated by a trigger signal called convert start (CONVST). Event-driven sampling mode is used when precise control over the sampling instant is necessary.

Figure 5-2: Event Driven Sampling Mode

X-Ref Target - Figure 5-2


The DCLK must always be present when using event-driven sampling mode. If no DCLK is present, the XADC reverts to continuous mode timing using an internal clock oscillator.

A Low-to-High transition (rising edge) on CONVST or CONVSTCLK defines the exact sampling instant for the selected analog-input channel. The BUSY signal transitions High just after the sampling instant on the next rising edge of DCLK. CONVST can be an asynchronous external signal in which case the XADC automatically resynchronizes the conversion process to the ADCCLK.

As with the continuous sampling mode, enough time must be allowed for the acquisition phase, that is, the time between a channel change and the sampling edge (the rising edge of CONVST or CONVSTCLK, see Analog Input Description, page 23 ). This allows the ADC to acquire the new signal before it is sampled by the CONVST signal and the conversion phase starts. A settling period of four ADCCLK cycles is recommended between the end of the current conversion (BUSY going Low) and the start of the next conversion. The ACQ bit has no meaning in event-sampling mode because the sampling instant is controlled by CONVST/CONVSTCLK. Therefore, the acquisition time on a selected channel is also controlled by CONVST/CONVSTCLK. CONVST and CONVSTCLK are logically ORed within the XADC. The T/H starts to acquire the voltage on the next channel as soon as BUSY goes High and a conversion starts.

After the analog input has been sampled by a rising edge on CONVST/CONVSTCLK, a conversion is initiated on the next rising edge of ADCCLK. After a conversion has been initiated by CONVST, it is not possible to interrupt the conversion or start a new conversion until BUSY goes Low.

16 DCLK cycles after BUSY goes Low, EOC pulses High for one DCLK cycle when the conversion result has been transferred to the output register. EOS indicates the end of a sequence that depends on the automatic channel sequencer settings and averaging settings. If the automatic channel sequencer is used, then EOS matches the last channel enabled (see Table 4-1 ). When averaging is used, EOS only pulses High after all the sequences or samples have been completed (16, 64, and 256). The number of samples is set by AVG0 and AVG1 in Configuration Reg #0 ( 40h ) (see Table 3-8 ).

Remember that CONVST/CONVSTCLK starts a single conversion. When using the automatic channel sequencer or averaging, the number of conversions are the product of the number of channels in a sequence and the number of samples being averaged.