Control Registers

The XADC has 32 control registers that are located at DRP addresses 40h to 5Fh (see Table 3-3 ). These registers are used to configure the XADC operation. All XADC functionality is controlled through these registers.

These control registers are initialized using the XADC attributes when the XADC is instantiated in a design. This means that the XADC can be configured to start in a predefined mode after FPGA configuration.

Table 3-3: XADC Control Registers
Name	Address	Software Attribute	Description
Configuration register 0	40h	INIT_40	These are XADC configuration registers (see Configuration Registers ( 40h to 42h ) ).
Configuration register 1	41h	INIT_41
Configuration register 2	42h	INIT_42
Test registers 0 to 4	43h to 47h	INIT_43 to INIT_47	These are test registers. The default initialization is 0000h . These registers are used for factory test and should be left at the default initialization.
Sequence registers	48h to 4Fh	INIT_48 to INIT_4F	These registers are used to program the channel sequencer function (see Chapter 4, XADC Operating Modes ).
Alarm registers	50h to 5Fh	INIT_50 to INIT_5F	These are the alarm threshold registers for the XADC alarm function (see Automatic Alarms, page 56 ).

Configuration Registers ( 40h to 42h )

The first three registers in the control register block configure the XADC operating modes. These registers are known as XADC configuration registers. Their bit definitions are illustrated in Figure 3-4 .

Note: Bits shown as 0 should always be left set to 0 .

The configuration registers can be modified through the DRP after the FPGA has been configured. For example, a soft microprocessor or state machine can be used to alter the contents of the XADC control registers at any time during normal operation. Table 3-4 through Table 3-6 define the bits for the three configuration registers.

Figure 3-4: Configuration Registers Bit Definitions
X-Ref Target - Figure 3-4

Notes relevant to Figure 3-4 :

1. Zynq-7000 SoC devices only.

Table 3-4: Configuration Register 0 Bit Definitions
Bit	Name	Description
DI0 to DI4	CH0 to CH4	When operating in single channel mode or external multiplexer mode, these bits are used to select the ADC input channel. See Table 3-7 for the channel assignments.
DI8	ACQ	When using single channel mode, this bit is used to increase the settling time available on external analog inputs in continuous sampling mode by six ADCCLK cycles (see Chapter 2, Analog-to-Digital Converter and Chapter 5, XADC Timing ). The acquisition time is increased by setting this bit to logic 1. (1)
DI9	E C	This bit is used to select either continuous or event-driven sampling mode for the ADC (see Chapter 5, XADC Timing ). A logic 1 places the ADC in event-driven sampling mode and a logic 0 places the ADC in continuous sampling mode.
DI10	B U	This bit is used in single channel mode to select either unipolar or bipolar operating mode for the ADC analog inputs (see Analog Inputs, page 21 ). A logic 1 places the ADC in bipolar mode and a logic 0 places the ADC in unipolar mode.
DI11	MUX	This bit should be set to a logic 1 to enable external multiplexer mode. See External Multiplexer Mode for more information.
DI12, DI13	AVG0, AVG1	These bits are used to set the amount of sample averaging on selected channels in both single channel and sequence modes (see Table 3-8 and Chapter 4, XADC Operating Modes ).
DI15	CAVG	This bit is used to disable averaging for the calculation of the calibration coefficients. Averaging is enabled by default (logic 0). To disable averaging, set this bit to logic 1. Averaging is fixed at 16 samples.
Notes: 1. Acquisition times for sequencer modes use channel sequencer registers; see ADC Channel Settling Time ( 4Eh and 4Fh ) in Chapter 4 .

Table 3-5: Configuration Register 1 Bit Definitions
Bit	Name	Description
DI0	OT	This bit is used to disable the over-temperature signal. The alarm is disabled by setting this bit to logic 1.
DI1 to DI3, DI8	ALM0 to ALM3	These bits are used to disable individual alarm outputs for temperature, V _CCIN _T , V _CCAU _X , and V _CCBRAM , respectively. A logic 1 disables an alarm output.
DI9 to DI11	ALM4 to ALM6	These bits are used to disable individual alarm outputs for V _CCPINT , V _CCPAUX , and V _{CCO_DDR} , respectively. A logic 1 disables an alarm output.
DI4 to DI7	CAL0 to CAL3	These bits enable the application of the calibration coefficients to the ADC and on-chip supply sensor measurements. A logic 1 enables calibration and a logic 0 disables calibration. For bit assignments, see Table 3-10 .
DI12 to DI15	SEQ0 to SEQ3	These bits enable the channel-sequencer function. For the bit assignments, see Table 3-9 . See Chapter 4, XADC Operating Modes , for more information.

Table 3-6: Configuration Register 2 Bit Definitions
Bit	Name	Description
DI4, DI5	PD0, PD1	Power-down bits for the XADC. The entire XADC block can be powered down permanently by setting PD1 = PD0 = 1 . ADC B can also be powered down permanently by setting PD1 = 1 and PD0 = 0 . See Table 3-11 .
DI8 to DI15	CD0 to CD7	These bits select the division ratio between the DRP clock (DCLK) and the lower frequency ADC clock (ADCCLK) used for the ADC (see Chapter 5, XADC Timing ). For bit assignments, see Table 3-12 .

Table 3-7: ADC Channel Select
ADC Channel	CH4	CH3	CH2	CH1	CH0	Description
0	0	0	0	0	0	On-chip temperature
1	0	0	0	0	1	V _CCINT
2	0	0	0	1	0	V _CCAUX
3	0	0	0	1	1	V _P , V _N – Dedicated analog inputs
4	0	0	1	0	0	V _REFP (1.25V) ⁽¹⁾
5	0	0	1	0	1	V _REFN (0V) ⁽¹⁾
6	0	0	1	1	0	V _CCBRAM
7	0	0	1	1	1	Invalid channel selection
8	0	1	0	0	0	Carry out an XADC calibration
9–12	...	...	...	...	...	Invalid channel selection
13	0	1	1	0	1	V _CCPINT ⁽³⁾
14	0	1	1	1	0	V _CCPAUX ⁽³⁾
15	0	1	1	1	1	V _{CCO_DDR} ⁽³⁾
16	1	0	0	0	0	VAUXP[0], VAUXN[0] – Auxiliary channel 0
17	1	0	0	0	1	VAUXP[1], VAUXN[1] – Auxiliary channel 1
18–31	...	...	...	...	...	VAUXP[2:15], VAUXN[2:15] – Auxiliary channels 2 to 15 ⁽²⁾
Notes: 1. These channel selection options are used for XADC self-check and calibration operations. When these channels are selected, the supply sensor is connected to V _REFP or V _REFN . 2. Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex ® -7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC package options. Users should consult the package file for the device. 3. These channels are only supported in Zynq-7000 SoC devices.

Table 3-8: Averaging Filter Settings
AVG1	AVG0	Function
0	0	No averaging
0	1	Average 16 samples
1	0	Average 64 samples
1	1	Average 256 samples

Table 3-9: Sequencer Operation Settings
SEQ3	SEQ2	SEQ1	SEQ0	Function
0	0	0	0	Default mode
0	0	0	1	Single pass sequence
0	0	1	0	Continuous sequence mode
0	0	1	1	Single channel mode (sequencer off)
0	1	X	X	Simultaneous sampling mode
1	0	X	X	Independent ADC mode
1	1	X	X	Default mode

Table 3-10: Calibration Enables
Name	Description
CAL0	ADCs offset correction enable
CAL1	ADCs offset and gain correction enable
CAL2	Supply sensor offset correction enable
CAL3	Supply sensor offset and gain correction enable

Table 3-11: Power Down Selection
PD1	PD0	Description
0	0	Default. All XADC blocks powered up
0	1	Not valid – do not select
1	0	ADC B powered down
1	1	XADC powered down

Table 3-12: DCLK Division Selection ⁽¹⁾ ⁽²⁾
CD7	CD6	CD5	CD4	CD3	CD2	CD1	CD0	Division
0	0	0	0	0	0	0	0	2
0	0	0	0	0	0	0	1	2
0	0	0	0	0	0	1	0	2
0	0	0	0	0	0	1	1	3
0	0	0	0	0	1	0	0	4
.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.
.	.	.	.	.	.	.	.	.
1	1	1	1	1	1	1	0	254
1	1	1	1	1	1	1	1	255
Notes: 1. Minimum division ratio is 2, for example, ADCCLK = DCLK/2. 2. DCLK division must be selected to keep the ADC clock in its supported frequency range as specified in the applicable data sheet. To find the data sheet, see the Xilinx website .

Test Registers ( 43h to 47h )

These registers, intended for factory test purposes only, have a default status of zero. You must not write to these registers.

Channel Sequencer Registers ( 48h to 4Fh )

These registers are used to program the channel sequencer functionality. For more information see Automatic Channel Sequencer, page 46 .

Alarm Registers ( 50h to 5Fh )

These registers are used to program the alarm thresholds for the automatic alarms on the internally monitored channels, temperature, V _CCINT , V _CCAUX , and V _CCBRAM . For Zynq-7000 SoC devices, the alarm thresholds for V _CCPINT , V _CCPAUX , and V _{CCO_DDR} are also set using these registers. For more information, see Automatic Alarms, page 56 .