Automatic Alarms

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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Automatic Alarms

The XADC also generates an alarm signal on the logic outputs ALM[7:0] when an internal sensor measurement (Temperature, V CCINT , V CCAUX , V CCBRAM , V CCPINT , V CCPAUX , or V CCO_DDR ) exceeds some user-defined thresholds. Only the values written to the status registers are used to generate alarms. If averaging has been enabled for a sensor channel, the averaged value is compared to the alarm threshold register contents. The alarm outputs are disabled by writing a 1 to bits ALM6 to ALM0 in configuration register 1. The alarm thresholds are stored in control registers 50h to 5Fh . Table 4-8 defines the alarm thresholds that are associated with specific control registers. The limits written to the threshold registers are MSB justified. Limits are derived from the temperature and power-supply sensor transfer functions (see Figure 2-9, page 26 and Figure 2-10, page 27 ).

Table 4-8: Alarm Threshold Registers

Control Register




Temperature upper



V CCINT upper



V CCAUX upper



OT alarm limit (1)



Temperature lower



V CCINT lower



V CCAUX lower



OT alarm reset (1)



V CCBRAM upper



V CCPINT upper (2)



V CCPAUX upper (2)



V CCO_DDR upper (2)



V CCBRAM lower



V CCPINT lower (2)



V CCPAUX lower (2)



V CCO_DDR lower (2)



1. OT alarm limit and OT alarm reset are described in Thermal Management .

2. Only Zynq-7000 SoC devices support these channels.

Supply Sensor Alarms

When the measured value on the supply sensor for V CCINT , V CCAUX , V CCBRAM , V CCPINT , V CCPAUX , or V CCO_DDR is greater than the thresholds in control registers 51h , 52h , 58h , 59h , 5Ah , and 5Bh or less than the thresholds in control registers 55h , 56h , 5Ch , 5Bh , 5D , and 5Eh , respectively, the output alarms go active. The alarms are reset when a subsequently measured value falls inside the threshold.

Thermal Management

The on-chip temperature measurement is used for critical temperature warnings and also supports automatic shutdown to help prevent the device from being permanently damaged. The on-chip temperature measurements record the junction temperatures continuously during pre-configuration and automatic shutdown.

Automatic shutdown must be enabled by setting the four LSBs (DI[3:0]) to 0011b in the OT upper alarm register ( 53h ) and by adding the following constraint to the project XDC file:


The default over temperature (OT) threshold is 125°C. The 125°C threshold is used when the contents of the OT upper alarm register ( 53h ) is 0000h , including pre-configuration. To override this default condition, the 12 MSBs of the OT upper register (control register 53h ) must be set using the temperature sensor transfer function (see Figure 2-10 ).

Equation 4-1 ug480_c4XADCOpModes00270.jpg

Equation 4-2 ug480_c4XADCOpModes00272.jpg

From Equation Equation 4-1 (in bits) or Equation Equation 4-2 for 125°C, control register 53h must be set to CA3h for the 12 MSBs. Because the four LSBs must be set to 3h , this gives the 16-bit register value of CA33h for control register 53h .

Equation 4-3 ug480_c4XADCOpModes00274.jpg

For the remaining temperature thresholds, use Equation 4-3 to define the 16-bit ADC code values.

Figure 4-4: Thermal Management Operation Example

X-Ref Target - Figure 4-4


As shown in Figure 4-4 , when the die temperature exceeds the OT upper threshold (or the default 125°C), the over-temperature alarm logic output becomes active and 10 ms later the device initiates the shutdown sequence. When the automatic shutdown starts, the device is disabled and GHIGH is asserted to prevent any contention (see UG470, 7 Series FPGAs Configuration User Guide [Ref 3] ). When OT is deasserted (50°C as shown in Figure 4-4 ), GHIGH is also deasserted and the start-up sequence is initiated releasing all global resources.

Note: When the OT alarm has been triggered in 7 series FPGAs, PROGRAM_B input levels are ignored until the die temperature resets the OT alarm (OT_Lower 57h ). That is, PROGRAM_B can only be used to reconfigure the FPGA after GHIGH has been deasserted.

While the device is shut down, XADC automatically uses the internal clock oscillator, but otherwise remains unchanged. JTAG is only guaranteed to 125°C.

The automatic shutdown feature is for preventing permanent damage to the device. After the temperature has fallen below the OT lower ( 57h ) setting and OT is deasserted, the device must be reconfigured. Additionally, because a catastrophic failure occurred, all power to the device should be removed and it should be determined why the device temperature increased so dramatically. Designs should use a thermal management procedure with the temperature alarm (ALM[0]) to actively control the device temperature during operation.

If XADC is instantiated, the automatic shutdown feature can be disabled either by setting the OT signal within Config Reg 1 ( 41h ) High, or by adding the following constraint to the project XDC file:


See UG908, Vivado Design Suite User Guide: Programming and Debugging [Ref 8] for additional details on device configuration bitstream settings. ENABLE and DISABLE are allowable values.

A second user-programmable temperature threshold level (temperature upper 50h ) is used to carry out a user-defined thermal management procedure, such as powering on or controlling the speed of a fan. Alarm signal ALM[0] is High when the device temperature exceeds the limit in the temperature upper control register 50h . ALM[0] remains High until the temperature falls below the lower threshold, temperature lower ( 54h ). As shown in Figure 4-4 , this means that ALM[0] is High when the temperature reaches 80°C and remains High until the temperature falls to 70°C. This operation differs for the supply sensor alarm because the supply alarm resets when the measurement is between the upper and lower thresholds.

XADC Enhanced Linearity Mode

For ISE design tools, a BitGen option called XADCEnhancedLinearity is available. It enhances the linearity (INL) and dynamic performance (SNR and THD) of the ADCs in the XADC block. This bitgen -g command line option is XADCEnhancedLinearity = [ON¦OFF]. By default this BitGen option is OFF. This mode was also OFF by default in all previous releases of the ISE design tools.

For the Vivado design tools, use XADCENHANCEDLINEARITY . See UG908, Vivado Design Suite User Guide: Programming and Debugging [Ref 8] for the XDC templates.

set_property BITSTREAM.GENERAL.XADCENHANCEDLINEARITY <On|Off> [current_design]

Changes to Offset and Gain Calibration Operation

If the XADCEnhancedLinearity option is not enabled (that is, OFF), there is no change to the XADC operation when offset and gain calibration is enabled. See XADC Calibration Coefficients, page 33 , for an explanation of how the ADC offset and gain calibration is enabled. However, if this new BitGen option is enabled, some differences in the ADC transfer functions are observed when offset and gain calibration coefficients are applied.

Figure 4-5: ADC Calibration with XADCEnhancedLinearity = ON

X-Ref Target - Figure 4-5


Figure 4-5 illustrates the impact of enabling offset and gain error correction with XADCEnhancedLinearity = ON . In this example, the red line shows the impact of offset and gain errors on the ADC transfer function. This is exaggerated for clarity. To remove the offset error, a constant correction (offset calibration coefficient) is subtracted from the ADC output. This is shown as the blue line in Figure 4-5 . The black solid line shows the impact of the gain error and offset correction. Because the ADC uncalibrated output reached full scale ( FFFh ) before the input reached 1V (due to offset and gain errors), part of the ADC transfer function is no longer available even after calibration. Thus, the ADC maximum code stays at a value less than FFFh even for input voltages of 1V. This clipping range is typically no more than about 10 mV around either 0V or 1V input, depending on the ADC offset and gain errors. For example, if the offset error was negative in the example shown in Figure 4-5 , ADC would produce a 0 code out until the analog input exceeded this offset with offset correction enabled.

Note: This clipping effect is not seen when the option XADCEnhancedLinearity = OFF .