External Analog Inputs

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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1.11 English

External Analog Inputs

The analog inputs are high-impedance differential inputs. The differential input scheme enables the rejection on common mode noise on any externally applied analog-input signal. Because of the high impedance of each input (such as V P and V N ), the input AC impedance is typically determined by the sensor, the output impedance of the driving circuitry, or other external components. Figure 6-3 illustrates a simple resistor divider network is used to monitor an external 2.5V supply rail in unipolar input mode. Analog-input traces on the PCB should also be routed as tightly coupled differential pairs.

Figure 6-3: Voltage Attenuation

X-Ref Target - Figure 6-3


See XAPP795, Driving the Xilinx Analog-to-Digital Converter Application Note [Ref 7] for more details. In Figure 6-3 , resistors R1 and R2 divide a 10V supply down to 1V to work with the XADC. R5 has been impedance matched to the parallel resistance of R1 and R2.

The anti-aliasing filter settling time for this example is determined by Equation 6-1 . With a resolution of 12 bits, the example components result in a settling time of 4.9 x10 –6 s or slightly faster than 200 Ks/s.

Equation 6-1 ug480_c6Guidelines00284.jpg

Anti-Alias Filters

Also shown in Figure 6-3 , is a low-pass filter network at the analog differential inputs. This filter network is commonly referred to as the anti-alias filter and should be placed as close as possible to the package pins. The sensor can be placed remotely from the package as long as the differential input traces are closely coupled. The anti-alias filter attenuates high-frequency signal components entering the ADC where they could be sampled and aliased, resulting in ADC measurement corruption. A discussion of aliasing in sampled systems is beyond the scope of this document. A good data converter reference book can provide more information on this topic.

Over and Under Voltages

The input voltage can exceed VCCADC (1.8V) or go below GNDADC by as much as 100 mV without damage to the XADC. To limit the current to 1.0 mA, a current-limiting resistor of at least 100 should be placed in series with the analog inputs. The resistors in the anti-alias filters fulfill this requirement. If the analog input range (1V) is exceeded, the ADC output code clips at the maximum output code shown in Figure 2-2, page 19 or Figure 2-3, page 20 , depending on the analog input mode. Negative input voltages clip at zero code.