Instantiating the XADC

As mentioned previously, it is not necessary to instantiate the XADC in a design to access the on-chip monitoring capability. However, if the XADC is not instantiated in a design, the only way to access this information is through the JTAG test access port (TAP). To allow access to the status registers (measurement results) from the FPGA logic, the XADC must be instantiated. These subsections give a brief overview of the XADC primitive (ports and attributes).

XADC Ports

Figure 1-3 shows the ports on the XADC primitive, and Table 1-2 describes the functionality of the ports.

Figure 1-3: XADC Primitive Ports
X-Ref Target - Figure 1-3

Table 1-2: XADC Port Descriptions
Port	I/O	Description
DI[15:0]	Inputs	Input data bus for the DRP. ⁽¹⁾
DO[15:0]	Outputs	Output data bus for the DRP. ⁽¹⁾
DADDR[6:0]	Input	Address bus for the DRP. ⁽¹⁾
DEN ⁽²⁾	Input	Enable signal for the DRP. ⁽¹⁾
DWE ⁽²⁾	Input	Write enable for the DRP. ⁽¹⁾
DCLK	Input	Clock input for the DRP. ⁽¹⁾
DRDY ⁽²⁾	Output	Data ready signal for the DRP. ⁽¹⁾
RESET ⁽²⁾	Input	Asynchronous reset signal for the XADC control logic. RESET will be deasserted synchronously to DCLK or the internal configuration clock when DCLK is stopped.
CONVST ⁽³⁾	Input	Convert start input. This input controls the sampling instant on the ADC(s) inputs and is only used in event mode timing (see Event-Driven Sampling, page 62 ). This input comes from the general-purpose interconnect in the FPGA logic.
CONVSTCLK ⁽³⁾	Input	Convert start clock input. This input is connected to a clock net. Like CONVST, this input controls the sampling instant on the ADC(s) inputs and is only used in event mode timing. This input comes from the local clock distribution network in the FPGA logic. Thus, for the best control over the sampling instant (delay and jitter), a global clock input can be used as the CONVST source.
V _P , V _N	Input	One dedicated analog input pair. The XADC has one pair of dedicated analog input pins that provide a differential analog input. When designing with the XADC feature but not using the dedicated external channel of V _P and V _N , you should connect both V _P and V _N to analog ground.
VAUXP[15:0], VAUXN[15:0]	Inputs	Sixteen auxiliary analog input pairs. In addition to the dedicated differential analog input, the XADC can access 16 differential analog inputs by configuring digital I/O as analog inputs. These inputs can also be enabled pre-configuration through the JTAG port (see DRP JTAG Interface, page 40 ).
ALM[0] ⁽²⁾	Output	Temperature sensor alarm output.
ALM[1] ⁽²⁾	Output	V _CCINT sensor alarm output.
ALM[2] ⁽²⁾	Output	V _CCAUX sensor alarm output.
ALM[3] ⁽²⁾	Output	V _CCBRAM sensor alarm output.
ALM[4] ⁽⁴⁾	Output	V _CCPINT sensor alarm output.
ALM[5] ⁽⁴⁾	Output	V _CCPAUX sensor alarm output.
ALM[6] ⁽⁴⁾	Output	V _{CCO_DDR} sensor alarm output.
ALM[7] ⁽²⁾	Output	Logic OR of bus ALM[6:0]. Can be used to flag the occurrence of any alarm.
OT ⁽²⁾	Output	Over-Temperature alarm output.
MUXADDR[4:0]	Outputs	These outputs are used in external multiplexer mode. They indicate the address of the next channel in a sequence to be converted. They provide the channel address for an external multiplexer (see External Multiplexer Mode, page 53 ).
CHANNEL[4:0]	Outputs	Channel selection outputs. The ADC input MUX channel selection for the current ADC conversion is placed on these outputs at the end of an ADC conversion.
EOC ⁽²⁾	Output	End of conversion signal. This signal transitions to active-High at the end of an ADC conversion when the measurement is written to the status registers (see Chapter 5, XADC Timing ).
EOS ⁽²⁾	Output	End of sequence. This signal transitions to active-High when the measurement data from the last channel in an automatic channel sequence is written to the status registers (see Chapter 5, XADC Timing ).
BUSY ⁽²⁾	Output	ADC busy signal. This signal transitions High during an ADC conversion. This signal also transitions High for an extended period during an ADC or sensor calibration.
JTAGLOCKED ⁽²⁾	Output	Indicates that a DRP port lock request has been made by the JTAG interface (see DRP JTAG Interface, page 40 ). This signal is also used to indicate that the DRP is ready for access (when Low).
JTAGMODIFIED ⁽²⁾	Output	Used to indicate that a JTAG write to the DRP has occurred.
JTAGBUSY ⁽²⁾	Output	Used to indicate that a JTAG DRP transaction is in progress.
Notes: 1. The DRP is the interface between the XADC and FPGA. All XADC registers can be accessed from the FPGA logic using this interface. For more details on the timing for these DRP signals, see Figure 5-3, page 64 . 2. Active-High signal. 3. Rising edge triggered signal. 4. Only available on Zynq-7000 SoC devices.

XADC Attributes

The block diagram in Figure 1-1 shows the control registers that define the operation of the XADC. The control registers are a set of 32 16-bit registers. As mentioned, these registers can be read and written through the DRP or JTAG ports. It is also possible to initialize the contents of these registers during the configuration of the FPGA. This enables the XADC to start operating in a user-defined mode after configuration is complete. There are 32 attributes associated with the XADC primitive that allow users to initialize these registers. Table 1-3 lists these attributes. The attributes are called INIT_xx, where xx corresponds to the hexadecimal address of the register on the DRP. For example, INIT_40 corresponds to the first control register at address 40h on the DRP.

Table 1-3: XADC Primitive Attributes
Attribute	Name	Control Register Address	Description
INIT_40	Configuration register 0	40h	XADC configuration registers (see Control Registers, page 35 ).
INIT_41	Configuration register 1	41h
INIT_42	Configuration register 2	42h
INIT_43 to INIT_47	Test registers	43h to 47h	XADC Test registers for factory use only. The default initialization is 0000h .
INIT_48 to INIT_4F	Sequence registers	48h to 4Fh	Sequence registers used to program the XADC Channel Sequencer function (see Automatic Channel Sequencer, page 46 ).
INIT_50 to INIT_5F	Alarm limit registers	50h to 5Fh	Alarm threshold registers for the XADC alarm function (see Automatic Alarms, page 56 ).

The XADC primitive also has an attribute called SIM_MONITOR_FILE that points to the analog stimulus file. This attribute is required to support simulation. This attribute points to the path and file name of a text file that contains analog information (for example, temperature and voltage). UNISIM and SIMPRIM models use this text file during simulation. This is the only way analog signals can be introduced into a simulation of the XADC. For more information see XADC Software Support, page 70 .

Example Instantiation

Instantiating the XADC involves connecting the required I/O (including analog inputs) to the design and optionally initializing the control registers to define the XADC operation after configuration. Alternatively, users can write to the control registers through the DRP after device configuration. The timing diagram for DRP read and write operations is shown in Figure 5-3 .

Note: The read/write operation is not valid or complete until the DRDY signal goes active.

This subsection provides a brief example of an XADC instantiation using Verilog. First, the control registers are initialized, and then the required XADC I/Os are connected to the design. The software correctly ties off unconnected I/Os on the primitive.

This design assumes an external 50 MHz clock is used for DCLK, and the XADC is configured to monitor temperature, supply voltages, and activate alarms if safe limits are exceeded. This example is explained in detail in XADC Software Support, page 70 .

XADC #(

// Initializing the XADC Control Registers

.INIT_40(16'h9000), // Calibration coefficient averaging disabled

// averaging of 16 selected for external channels

.INIT_41(16'h2ef0), // Continuous Sequencer Mode, Disable unused ALMs,

// Enable calibration

.INIT_42(16'h0400), // Set DCLK divider to 4, ADC = 500Ksps, DCLK = 50MHz

.INIT_48(16'h4701), // Sequencer channel - enable Temp sensor, VCCINT, VCCAUX,

// VCCBRAM, and calibration

.INIT_49(16'h000f), // Sequencer channel - enable aux analog channels 0 - 3

.INIT_4A(16'h4700), // Averaging enabled for Temp sensor, VCCINT, VCCAUX,

// VCCBRAM

.INIT_4B(16'h0000), // No averaging on external channels

.INIT_4C(16'h0000), // Sequencer Bipolar selection

.INIT_4D(16'h0000), // Sequencer Bipolar selection

.INIT_4E(16'h0000), // Sequencer Acq time selection

.INIT_4F(16'h0000), // Sequencer Acq time selection

.INIT_50(16'hb5ed), // Temp upper alarm trigger 85°C

.INIT_51(16'h5999), // Vccint upper alarm limit 1.05V

.INIT_52(16'hA147), // Vccaux upper alarm limit 1.89V

.INIT_53(16'h0000), // OT upper alarm limit 125°C using automatic shutdown

.INIT_54(16'ha93a), // Temp lower alarm reset 60°C

.INIT_55(16'h5111), // Vccint lower alarm limit 0.95V

.INIT_56(16'h91Eb), // Vccaux lower alarm limit 1.71V

.INIT_57(16'hae4e), // OT lower alarm reset 70°C

.INIT_58(16'h5999), // VCCBRAM upper alarm limit 1.05V

.INIT_5C(16'h5111), // VCCBRAM lower alarm limit 0.95V

.SIM_MONITOR_FILE("sensor_input.txt")

// Analog Stimulus file. Analog input values for simulation

)

XADC_INST ( // Connect up instance IO. See UG480 for port descriptions

.CONVST(GND_BIT), // not used

.CONVSTCLK(GND_BIT), // not used

.DADDR(DADDR_IN[6:0]),

.DCLK(DCLK_IN),

.DEN(DEN_IN),

.DI(DI_IN[15:0]),

.DWE(DWE_IN),

.RESET(RESET_IN),

.VAUXN(aux_channel_n[15:0]),

.VAUXP(aux_channel_p[15:0]),

.ALM(alm_int),

.BUSY(BUSY_OUT),

.CHANNEL(CHANNEL_OUT[4:0]),

.DO(DO_OUT[15:0]),

.DRDY(DRDY_OUT),

.EOC(EOC_OUT),

.EOS(EOS_OUT),

.JTAGBUSY(), // not used

.JTAGLOCKED(), // not used

.JTAGMODIFIED(), // not used

.OT(OT_OUT),

.MUXADDR(), // not used

.VP(VP_IN),

.VN(VN_IN)

);

ADC and Sensors

More comprehensive information regarding the operation of the ADCs and on-chip sensors can be found in Chapter 2, Analog-to-Digital Converter . This section provides a brief overview to help users to quickly interpret data read from the status registers and verify the operation of the XADC.

Analog-to-Digital Converter

The ADCs have a nominal analog input range from 0V to 1V. In unipolar mode (default), the analog inputs of the ADCs produce a full scale code of FFFh (12 bits) when the input is 1V. Thus, an analog input signal of 200 mV in unipolar mode produces and outputs code of Equation 1-1 .

Equation 1-1

In bipolar mode, the ADCs use two’s complement coding and produces a full scale code of 7FFh with +0.5V input and 800h with –0.5V input.

Temperature Sensor

The temperature sensor has a transfer function given by Equation 1-2 .

Equation 1-2

For example, ADC Code 2423 ( 977h ) = 25°C.

The temperature sensor result can be found in status register 00h .

Power Supply Sensors

The XADC power supply sensors have a transfer function that generates a full scale ADC output code of FFFh with a 3V input voltage. This voltage is outside the allowed supply range, but the FPGA supply measurements map into this measurement range. Thus, V _CCINT = 1V generates an output code of 1/3 x 4096 = 1365 = 555h . The XADC monitors V _CCINT , V _CCAUX , and V _CCBRAM . The measurement results are stored in status registers 01h , 02h , and 06h , respectively.

Zynq-7000 SoC

The XADC monitors three additional power supplies on the Zynq-7000 SoC devices. The supplies are V _CCPINT , V _CCPAUX , and V _{CCO_DDR} . These measurements are stored in status registers 0Dh , 0Eh , and 0Fh , respectively.

Instantiating the XADC - UG480

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)