XADC Timing

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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1.11 English

Chapter 5

XADC Timing

All XADC timing is synchronized to the DRP clock (DCLK). The ADCCLK is generated by dividing DCLK by the user selection in configuration register 2 (see Control Registers, page 35 ). ADCCLK is an internal clock used by the ADCs and is not available externally. ADCCLK is only included here to aid in describing the timing.

The ADC block is operated in one of two possible timing modes, continuous sampling mode and event driven sampling mode.

In continuous sampling mode, the ADC automatically starts a new conversion at the end of a current conversion cycle. In event sampling mode, you must initiate the next conversion after the current conversion cycle ends by using the CONVST or CONVSTCLK inputs. The operating mode is selected by writing to configuration register 0 (see Control Registers ).

Refer to the respective 7 series FPGAs data sheet for the latest XADC timing specifications. The robust nature of the XADC ensures continued and correct operation even if the external clock input DCLK is stopped. In this situation, the XADC automatically switches over to an internal clock oscillator to continue to operate as configured. After configuration, the DCLK input requires 20 DCLKs to resynchronize to the external clock. The JTAGLOCKED signal is High during this period. It is not possible to access the DRP until resynchronization has occurred.