PC Board Design Guidelines

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

Document ID
UG480
Release Date
2022-06-09
Revision
1.11 English

PC Board Design Guidelines

Figure 6-4 and Figure 6-5 illustrate one possible way to address the requirements outlined in the previous sections. Figure 6-4 shows how, by staggering the vias with respect to the pads, north-south and east-west routing channels through the via field are created. These routing channels can be used to bring tightly coupled differential pairs into the center of the via field, even when using 5 mil tolerances.

Figure 6-4: Routing Channels to Center of Array Created by Staggering Vias

X-Ref Target - Figure 6-4

X17044-routing-channels.jpg

Figure 6-5: Reference Inputs (V REFP and V REFN ) should be Routed as Differential Pairs into the Center of the BGA

X-Ref Target - Figure 6-5

X17045-reference-inputs.jpg

Notes relevant to Figure 6-5 :

1. Place anti-alias filters for analog inputs close to the FPGA.

2. Place 100 nF decoupling for V REFP and V CCADC here.

3. Place external reference IC and any dedicated analog power supply regulation as close to the FPGA as possible.

In Figure 6-5 , the pads have been removed for clarity. The reference inputs (V REFP and V REFN ) are routed as a tightly coupled differential pair from an external 1.25V reference IC at the bottom edge of the FPGA (refer to Figure 6-1 for the connections). The analog power supply and ground reference are also routed into the center of the BGA using traces. No power planes are required to supply a ground reference for the XADC. The analog supply and ground reference are connected to the external reference IC as shown in Figure 6-1 . In the PCB implementation shown, the supply and ground traces are routed on either side of the reference traces on the same signal layer and act as guards between the reference traces and any potential aggressors (for example, clocks and switching I/Os). It is not a requirement that the supply and ground traces are routed on the same signal layer as shown, but they should be routed on an adjacent layer. The V REFN and GNDADC traces should be connected at (or close to) the ground pin of the reference IC. The ferrite bead that connects the analog ground trace to system ground should also be placed close to the reference IC. Figure 6-5 also shows the routing (from the top) of the dedicated analog input pair (V P and V N ). These inputs are also routed as a differential pair.

The external reference IC should be placed as close as possible to the FPGA to reduce the opportunities for coupled noise and to minimize any impedances in the reference traces. The staggered via field also allows the 100 nF decoupling on V REFP and V CCADC to be placed in the center of the array close to the package balls. V REFP should be decoupled to V REFN and V CCADC to GNDADC near the package balls.

When using the on-chip reference, the layout of the PCB is greatly simplified. The V REFP and V REFN pins should be shorted to AGND locally at the package balls. The ferrite beads used to separate AGND and digital GND should be placed close to the XADC balls in the center of the array along with a 100 nF decoupling capacitor for V CCADC .

These suggestions are only intended to guide a low-cost PC board implementation. If it is feasible to create an analog reference plane, then there is no issue with doing this and it helps improve the ADC performance. However, the reference inputs should still be routed as differential pairs as shown. See the schematics and layout for the KC705 and AC701 evaluation boards for an example of a practical layout implementation. For more information, see XAPP554, XADC Layout Guidelines Application Note [Ref 6] .

XADC Software Support

This section explains in more detail the example shown in Example Instantiation, page 15 . The Verilog and VHDL source code and test benches for this example can be found in the ZIP file ug480_7Series_XADC.zip that accompanies this user guide:

Design file for UG480 ug480_7Series_XADC.zip

In addition to instantiating a basic design, the use of the Analog Stimulus file as a means to introduce analog signals into the simulation is also explained. Finally, the output of a simple behavioral simulation of the design is shown. The project illustrates an instantiation and simulation of the XADC in Vivado.

Using XADC Instantiation Wizard

One of the easiest methods to add the XADC to a design is to use the XADC instantiation wizard in the CORE Generator™ tool. In Vivado tools, the XADC Wizard can be found under the IP Catalog. The wizard is a GUI that allows designers to select the required block I/O and initialize the control registers for the required operation.

For more information on the XADC wizard, see PG091, XADC Wizard LogiCORE IP Product Guide for Vivado Design Suite [Ref 5] .

Example Design Instantiation

The following HDL example sets up the XADC to monitor all the FPGA on-chip sensors, that is, Temperature, V CCINT , V CCAUX , and V CCBRAM of a 7 series FPGA. See Temperature Sensor, page 17 and Power Supply Sensors, page 17 . In addition, four auxiliary analog input channels are also monitored. The XADC is also set to automatically generate alarm outputs when the defined operating ranges for the FPGA supply voltages and temperature are exceeded (see Automatic Alarms, page 56 ). The XADC is operated in continuous sequence mode for this example (see Sequencer Modes, page 49 ). For clarity (and shorter simulations), the averaging function is disabled by the test bench. Averaging does not have any impact on the simulation results because an ideal model of the XADC is used. It is recommended that averaging is enabled when monitoring the on-chip sensors in a typical application to minimize any noise impacts. This is especially true if the automatic alarm functions are used. Averaging has been enabled for the on-chip sensors in the instantiation shown below.

During simulation, if a design uses calibration, calibration coefficients will assume ideal conditions.

Apart from initializing the alarm threshold registers and the automatic channel sequencer register, the configuration registers need to be initialized to enable alarm outputs, sequencer modes, and the ADC clock divider (see Configuration Registers ( 40h to 42h ), page 36 for more information). Here is an instantiation in Verilog of the XADC example design:

`timescale 1ns / 1ps

module ug480 (

input DCLK, // Clock input for DRP

input RESET,

input [3:0] VAUXP, VAUXN,  // Auxiliary analog channel inputs

input VP, VN,// Dedicated and Hardwired Analog Input Pair

output reg [15:0] MEASURED_TEMP, MEASURED_VCCINT,

output reg [15:0] MEASURED_VCCAUX, MEASURED_VCCBRAM,

output reg [15:0] MEASURED_AUX0, MEASURED_AUX1,

output reg [15:0] MEASURED_AUX2, MEASURED_AUX3,

output wire [7:0] ALM,

output wire [4:0] CHANNEL,

output wire OT,

output wire EOC,

output wire EOS

);

wire busy;

wire [5:0] channel;

wire drdy;

reg [6:0] daddr;

reg [15:0] di_drp;

wire [15:0] do_drp;

wire [15:0] vauxp_active;

wire [15:0] vauxn_active;

wire eos;

wire eoc;

reg [1:0]  den_reg;

reg [1:0]  dwe_reg;

reg [7:0]   state = init_read;

parameter       init_read       = 8'h00,

read_waitdrdy   = 8'h01,

write_waitdrdy  = 8'h03,

read_reg00      = 8'h04,

reg00_waitdrdy  = 8'h05,

read_reg01      = 8'h06,

reg01_waitdrdy  = 8'h07,

read_reg02      = 8'h08,

reg02_waitdrdy  = 8'h09,

read_reg06      = 8'h0a,

reg06_waitdrdy  = 8'h0b,

read_reg10      = 8'h0c,

reg10_waitdrdy  = 8'h0d,

read_reg11      = 8'h0e,

reg11_waitdrdy  = 8'h0f,

read_reg12      = 8'h10,

reg12_waitdrdy  = 8'h11,

read_reg13      = 8'h12,

reg13_waitdrdy  = 8'h13;

always @(posedge DCLK)

if (RESET) begin

state   <= init_read;

den_reg <= 2'h0;

dwe_reg <= 2'h0;

di_drp  <= 16'h0000;

end

else

case (state)

init_read : begin

daddr = 7'h40;

den_reg = 2'h2; // performing read

if (busy == 0 ) state <= read_waitdrdy;

end

read_waitdrdy :

if (drdy ==1) begin

di_drp = do_drp  & 16'h03_FF; //Clearing AVG bits for Configreg0

daddr = 7'h40;

den_reg = 2'h2;

dwe_reg = 2'h2; // performing write

state = write_waitdrdy;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

write_waitdrdy :

if (drdy ==1) begin

state = read_reg00;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg00 : begin

daddr   = 7'h00;

den_reg = 2'h2; // performing read

if (eos == 1) state   <=reg00_waitdrdy;

end

reg00_waitdrdy :

if (drdy ==1) begin

MEASURED_TEMP = do_drp;

state <=read_reg01;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg01 : begin

daddr   = 7'h01;

den_reg = 2'h2; // performing read

state   <=reg01_waitdrdy;

end

reg01_waitdrdy :

if (drdy ==1) begin

MEASURED_VCCINT = do_drp;

state <=read_reg02;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg02 : begin

daddr   = 7'h02;

den_reg = 2'h2; // performing read

state   <=reg02_waitdrdy;

end

reg02_waitdrdy :

if (drdy ==1) begin

MEASURED_VCCAUX = do_drp;

state <=read_reg06;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg06 : begin

daddr   = 7'h06;

den_reg = 2'h2; // performing read

state   <=reg06_waitdrdy;

end

reg06_waitdrdy :

if (drdy ==1) begin

MEASURED_VCCBRAM = do_drp;

state <= read_reg10;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg10 : begin

daddr   = 7'h10;

den_reg = 2'h2; // performing read

state   <= reg10_waitdrdy;

end

reg10_waitdrdy :

if (drdy ==1) begin

MEASURED_AUX0 = do_drp;

state <= read_reg11;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg11 : begin

daddr   = 7'h11;

den_reg = 2'h2; // performing read

state   <= reg11_waitdrdy;

end

reg11_waitdrdy :

if (drdy ==1) begin

MEASURED_AUX1 = do_drp;

state <= read_reg12;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg12 : begin

daddr   = 7'h12;

den_reg = 2'h2; // performing read

state   <= reg12_waitdrdy;

end

reg12_waitdrdy :

if (drdy ==1) begin

MEASURED_AUX2= do_drp;

state <= read_reg13;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

read_reg13 : begin

daddr   = 7'h13;

den_reg = 2'h2; // performing read

state   <= reg13_waitdrdy;

end

reg13_waitdrdy :

if (drdy ==1) begin

MEASURED_AUX3= do_drp;

state <=read_reg00;

daddr   = 7'h00;

end

else begin

den_reg = { 1'b0, den_reg[1] } ;

dwe_reg = { 1'b0, dwe_reg[1] } ;

state = state;

end

endcase

XADC #(// Initializing the XADC Control Registers

.INIT_40(16'h9000),// averaging of 16 selected for external channels

.INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration

.INIT_42(16'h0400),// Set DCLK divides

.INIT_48(16'h4701),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration

.INIT_49(16'h000f),// CHSEL2 - enable aux analog channels 0 - 3

.INIT_4A(16'h0000),// SEQAVG1 disabled

.INIT_4B(16'h0000),// SEQAVG2 disabled

.INIT_4C(16'h0000),// SEQINMODE0

.INIT_4D(16'h0000),// SEQINMODE1

.INIT_4E(16'h0000),// SEQACQ0

.INIT_4F(16'h0000),// SEQACQ1

.INIT_50(16'hb5ed),// Temp upper alarm trigger 85°C

.INIT_51(16'h5999),// Vccint upper alarm limit 1.05V

.INIT_52(16'hA147),// Vccaux upper alarm limit 1.89V

.INIT_53(16'h0000),// OT upper alarm limit 125°C using automatic shutdown - see Thermal      Management

.INIT_54(16'ha93a),// Temp lower alarm reset 60°C

.INIT_55(16'h5111),// Vccint lower alarm limit 0.95V

.INIT_56(16'h91Eb),// Vccaux lower alarm limit 1.71V

.INIT_57(16'hae4e),// OT lower alarm reset 70°C - see Thermal Management

.INIT_58(16'h5999),// VCCBRAM upper alarm limit 1.05V

.SIM_MONITOR_FILE("design.txt")// Analog Stimulus file for simulation

)

XADC_INST (// Connect up instance IO. See UG480 for port descriptions

.CONVST (1'b0),// not used

.CONVSTCLK  (1'b0), // not used

.DADDR  (daddr),

.DCLK   (DCLK),

.DEN    (den_reg[0]),

.DI     (di_drp),

.DWE    (dwe_reg[0]),

.RESET  (RESET),

.VAUXN  (vauxn_active ),

.VAUXP  (vauxp_active ),

.ALM    (ALM),

.BUSY   (busy),

.CHANNEL(CHANNEL),

.DO     (do_drp),

.DRDY   (drdy),

.EOC    (EOC),

.EOS    (EOS),

.JTAGBUSY   (),// not used

.JTAGLOCKED (),// not used

.JTAGMODIFIED   (),// not used

.OT     (OT),

.MUXADDR    (),// not used

.VP     (VP),

.VN     (VN)

);

assign vauxp_active = {12'h000, VAUXP[3:0]};

assign vauxn_active = {12'h000, VAUXN[3:0]};

assign EOC = eoc;

assign EOS = eos;

endmodule

Example Design Test Bench

The following is a simple test bench that sets up a DCLK of 50 MHz and then reads the status registers (conversion results) at the end of a sequence when EOS goes High. The test bench also does a write to the DRP after the reset to disable the averaging on the sensor channels. The test bench monitors the alarm outputs so alarm events can be seen. Analog signals are not introduced into the simulation using the test bench. Analog signals are read from a file by the simulation model. The SIM_MONITOR_FILE attribute used in the XADC instantiation points the model to the location of this file known as the Analog Stimulus file . The Analog Stimulus file used for this example is shown here:

TIME VAUXP[0] VAUXN[0] VAUXP[1] VAUXN[1] VAUXP[2] VAUXN[2] VAUXP[3] VAUXN[3] Temp VCCINT VCCAUX VCCBRAM

00000   0.005   0.0     0.200   0.0      0.50    0.0       0.1     0.0      25   1.00    1.80    1.00

34000   0.020   0.0     0.400   0.0      0.49    0.0       0.2     0.0      85   1.05    1.90    1.05

67000   0.049   0.0     0.600   0.0      0.51    0.0       0.5     0.0      20   0.95    1.71    0.95

99999   0.034   0.0     0.900 0.0      0.53    0.0 0.0 0.0     125 1.00    1.80    1.00

The format of the analog stimulus file is based on space- or tab-delimited data and can be created in a spreadsheet, for example. Many tools such as SPICE simulators or even equipment such as oscilloscopes export comma-separated value (CSV) formats, which are manipulated in a spreadsheet to generate an analog stimulus file for simulation. All time stamp information must be listed in the first column. Other columns list the analog values for the on-chip sensors and external analog inputs. The order of the columns is not important, the only requirement is that time stamp information is listed in the first column. For every time stamp added to the first column, a corresponding value is added to the other columns. Only the required analog input channel columns need to be listed. In this example, only the on-chip sensors and auxiliary channels 0 to 3 are listed in the analog stimulus file. In this stimulus file, the voltage on V CCAUX moves from nominal supply (1.8V) to 1.9V at 27 µs after the start of the simulation. The V CCAUX_ALARM output can be seen to go active-High shortly after this event when the V CCAUX supply is measured by the ADC during the sequence (see Figure 6-6, page 77 ). The upper alarm threshold for V CCAUX has been set at 1.89V in the instantiation above.

`timescale 1ns / 1ps

module ug480_tb;

reg [3:0]      VAUXP, VAUXN;

reg             RESET;

reg             DCLK;

wire [15:0]     MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX;

wire [15:0]     MEASURED_VCCBRAM, MEASURED_AUX0, MEASURED_AUX1;

wire [15:0]     MEASURED_AUX2, MEASURED_AUX3;

wire [15:0]     ALM;

initial

begin

DCLK = 0;

RESET = 1;

#100    RESET = 0;

end

always #(10) DCLK= ~DCLK;

// Instantiate the Unit Under Test (UUT)

ug480 uut (

.VAUXP  (VAUXP),

.VAUXN  (VAUXN),

.RESET  (RESET),

.ALM  (ALM),

.DCLK   (DCLK),

.MEASURED_TEMP    (MEASURED_TEMP),

.MEASURED_VCCINT  (MEASURED_VCCINT),

.MEASURED_VCCAUX  (MEASURED_VCCAUX),

.MEASURED_VCCBRAM (MEASURED_VCCBRAM),

.MEASURED_AUX0    (MEASURED_AUX0),

.MEASURED_AUX1    (MEASURED_AUX1),

.MEASURED_AUX2    (MEASURED_AUX2),

.MEASURED_AUX3    (MEASURED_AUX3)

);

endmodule

Simulation Output

The simulation output shown in Figure 6-6 shows two passes through the user-defined sequence in continuous sampling mode. The channels monitored in the sequence can be seen by looking at the CHANNEL[4:0] bus. The sequence is 8, 0, 1, 2, 3, 6, 10, 11, 12, and 13, which corresponds to Calibration, Temperature, V CCINT , V CCAUX , V CCBRAM , Aux0, Aux1, Aux2, and Aux3. Then the sequence repeats. Note how the calibration channel takes longer to complete than the other channels. This is because the calibration routine involves three conversions (measurements) using the ADCs.

Figure 6-6: XADC Simulation Output (iSim)

X-Ref Target - Figure 6-6

X17046-xadc-simulation-output-iSim.jpg

After RESET goes Low, the test bench carries out a DRP write to register 40h (Configuration Register 0) to set the AVG1 and AVG0 bits to 00 (see Figure 6-7 ). This disables the averaging functionality for simulation.

Figure 6-7: DRP Write

X-Ref Target - Figure 6-7

X17047-drp-write.jpg

When the EOS signal pulses high for one DCLK period at the end of a sequence (at approximately 30 µs) the test bench reads the Status registers (see Figure 6-8 ). Note that the simulation model uses the full 16 ADC conversion result because it is an ideal model of the ADC. Thus for example, the result for the V CCINT measurement is 5555h , which corresponds to 1V. In Figure 2-10, page 27 ( Ideal Power Supply Transfer Function ) 1V is shown as 555h . This is a 12-bit MSB justified result. However, the 4 LSBs of the Status register also contain data that would be 5h if the ADC was an ideal 16-bit ADC.

Figure 6-8: DRP Read of Status Register at EOS

X-Ref Target - Figure 6-8

X17063-drp-read-status-register-eos.jpg

Note how the V CCAUX_ALARM output goes high during the second pass through the sequence ( Figure 6-6 ). The alarm goes active at the end of the conversion on the V CCAUX channel when the result is loaded in the Status register. The result is read from the Status register by the test bench when EOS next goes high. The V CCAUX is ~1.9V (as set in the stimulus file) and is greater than the 1.89V limit set when the XADC was instantiated in the design which activates the alarm.