External Multiplexer Mode

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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External Multiplexer Mode

The XADC supports the use an external analog multiplexer to implement several external analog inputs in situations where FPGA I/O resources are limited and auxiliary analog inputs are not available.

The XADC track/hold amplifiers return to track mode as soon as a conversion starts (see Figure 4-3 ). Therefore, the acquisition on the next channel can start during the current conversion cycle. An output bus called MUXADDR[4:0] allows the XADC to control an external multiplexer. The address on this bus reflects the channel currently being acquired, and it changes state as soon as the XADC enters acquisition mode. Users can also nominate the channel to be used with an external multiplexer.

External Multiplexer Operation

Figure 4-1 illustrates the external multiplexer concept. In this example an external 16:1 analog multiplexer is used instead of consuming the 32 FPGA I/Os required to implement the 16 auxiliary analog input channels using the internal multiplexer. Any four FPGA I/Os can be used for the external multiplexer decode operation. As shown in Figure 4-1 , the dedicated analog inputs (V P /V N ) are used to connect the external multiplexer to the XADC block, thereby making 16 analog inputs available. The external multiplexer mode of operation is enabled by setting the MUX bit in Configuration Register 0 (see Control Registers, page 35 ).

Figure 4-1: External Multiplexer Mode

X-Ref Target - Figure 4-1


When the MUX bit is set to a 1 , the channel selection bits (CH0 to CH4) in Configuration Register 0 are used to nominate the channel for connection to the external multiplexer. For example, as shown in Figure 4-1 , the dedicated analog input channel V P /V N is used. In this case, channel 3 ( 00011b ) should be written to CH4 to CH0 in Control Register 40h . Any one of the auxiliary channels can also be used for connection to the external multiplexer. In the case of simultaneous sampling mode (see Simultaneous Sampling Mode, page 50 ), two channels must be allocated to two external multiplexers to support simultaneous sampling.

Figure 4-2 illustrates how the external multiplexer mode is implemented for simultaneous sampling mode. The channels selected for connection are also selected by writing to CH4 to CH0 but are allocated in pairs as defined in Table 4-4 . For example, writing 16 ( 10000 ) to CH4 to CH0 would select auxiliary channels 0 and 8 for connection to external multiplexers as shown in Figure 4-2 .

Figure 4-2: External Multiplexer Mode for Simultaneous Sampling

X-Ref Target - Figure 4-2


In both cases, the MUXADDR[4:0] bus is used to automatically select the external multiplexer channel. Figure 4-3 shows how the MUXADDR bus reflects the next channel selection (N + 1). MUXADDR changes state eight ADCCLK cycles after BUSY goes High.

Figure 4-3: External Multiplexer Timing (Continuous Sampling Mode)

X-Ref Target - Figure 4-3