Single Channel Mode

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

Document ID
UG480
Release Date
2022-06-09
Revision
1.11 English

Single Channel Mode

This mode is enabled when bits SEQ3 to SEQ0 in control register 41h are set to 0011 (see Table 3-9, page 39 ). In this mode, you must select the channel for analog-to-digital conversion by writing to bit locations CH4 to CH0 in control register 40h . Various configurations for single channel mode, such as analog input mode (B U ) and settling time (ACQ), must also be set by writing to control register 40h . In applications where many channels need to be monitored, there can be a significant overhead for the microprocessor or other controller. To automate this task, a function called the automatic channel sequencer is provided.