Revision History

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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1.11 English

Revision History

The following table shows the revision history for this document.






Initial Xilinx release.



Added “Dual 12-Bit MSPS Analog-to-Digital Converter” to document title. Modified first paragraph and added second paragraph in Chapter 1, Introduction and Quick Start . Added Table 1-1 . Removed the Thermal Diode (DXP and DXN) section from Chapter 4.



This version was updated to include information for the Zynq-7000 SoC devices: Added “Zynq-7000 SoC” to document title.

In Figure 1-1 Zynq-7000 SoC information was added and the control and status registers changed from 32 x 16 bits to 64 x 16 bits. The System Monitor Support section changed to Differences between Virtex-5 and Virtex-6 System Monitors . Functionality for the XADC block in 7 series FPGAs is now defined for previously undefined status registers in subsequent chapters. Capacitor values in Figure 1-2 changed, and a note was added about the placement of 100 nF decoupling capacitors. In Table 1-1 , for V REFP_0 , GND changed to GNDADC, accurate reference source changed to accurate reference IC , and V P_0 and V N_0 types were changed to dedicated analog inputs. Footnotes were added to support 7 series and Zynq device pin packages. A note about application guidelines was added after Table 1-1 . Information about auxiliary analog channels was added to the External Analog Inputs section. In Table 1-2 , ports ALM[0] through [ALM[3] have XADC removed from the description. Alarms specific to Zynq-7000 SoC devices (ALM[4], ALM[5], and ALM[6]) were added. The example in Example Instantiation was updated. In ADC and Sensors , information about an analog input signal of 200 mV was modified, and Equation 1-1 was added. A new Zynq-7000 SoC subsection was added to the end of the chapter.

In ADC Transfer Functions MSBs are defined as left-most bits. In Auxiliary Analog Inputs in the instantiation was changed to on the primitive , and information that configuration is automatic when analog inputs are connected was added. The Note on page 22 was expanded to clarify device support of auxiliary analog channels. Equation 2-2 was added (unipolar mode), Equation 2-1 , Equation 2-3 , and Equation 2-4 were modified (“10”was changed to “9”), and the paragraph following Equation 2-4 was added. Information about additional external resistance was added to Unipolar Input Signals . In Temperature Sensor this sentence was deleted: “The on-chip temperature sensor has a maximum measurement error of ±4°C over a range of –40°C to +125°C.” Information was added to the Power Supply Sensor section about which supplies are monitored and where measurements are stored for Zynq-7000 SoC devices.



Min/max register lists were updated for Zynq-7000 SoC devices in Figure 3-1 . In Table 3-1 the V REFN description was updated, new Zynq-7000 device channels V CCPINT , V CCPAUX , and V CCO_DDR were added. Zynq-7000 SoC status registers were added to Figure 3-1 . Flag registers for DI5 through DI8 in Figure 3-2 changed and DIS was removed from Table 3-2 . XADC Calibration Coefficients were added. Configuration registers ALM[4], ALM[5], and ALM[6] were added to Figure 3-4 . In Table 3-3 , a new row was added for bits DI19 to DI11. In Table 3-7 , rows for ADC channels 13, 14, and 15 were added. Zynq-7000 SoC alarm threshold register information was added to Alarm Registers ( 50h to 5Fh ) . A note in the section DRP JTAG Interface mentions conditions in which the external JTAG access is disabled for Zynq devices. Section Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface was added to the end of the chapter.

In XADC Operating Modes , operate both ADCs in parallel in the first paragraph changed to operate both ADCs in lock step . In Single Channel Mode , the first sentence was deleted (“Single channel mode is the most basic way users can modify the operation of the XADC.”) Sequence numbers and descriptions in Table 4-1 and Table 4-2 changed and were added for Zynq-7000 SoC devices. In Sequencer Modes , default mode sequences were changed in Table 4-3 and added for Zynq-7000 SoC devices. The sentence before Table 4-4 was deleted. The footnote in Table 4-4 and Table 4-6 was enhanced to mention auxiliary analog channel support. Table 4-7 was updated to include Zynq-7000 SoC channels. Alarm threshold registers for the Zynq-7000 SoC were added to Table 4-8 . A new section XADC Enhanced Linearity Mode and Figure 4-5 were added to the end of the chapter.

The Dynamic Reconfiguration Port (DRP) Timing section was added. Removed Table 5-1: XADC Timing Information.

In Reference Inputs (V REFP and V REFN ) , added “Noise on the reference voltage also adds noise to the ADC conversion and results in more code transition noise or poorer than expected SNR” to the end of the first paragraph. Capacitor values were changed, a new 10 µF capacitor was added, and notes were added to Figure 6-1 . Notes were added to Figure 6-5 . XADC Software Support was completely replaced. In that section, the Verilog instantiation was replaced. Figure  6-6: Analog Stimulus File and Figure 6-7: XADC Simulation Output were deleted. In the new section, Figure 6-5 through Figure 6-8 were added.



Updated the disclaimer and copyright. Changes to Figure 1-2 in XADC Pinout Requirements . In External Analog Inputs , clarified how auxiliary analog inputs are handled in Vivado tools. Improved description of RESET signal in Table 1-2 . In Adjusting the Acquisition Settling Time , added to description of ACQ bit. In Analog Input Description , added note to Equation 2-1 . Added Table 3-3 , Calibration Coefficients in Status Register. Added to description of DI4 and DI5 in Table 3-5 . Added to important note in DRP JTAG Interface. Added clarification to Table 4-1 and Table 4-2 in ADC Channel Selection Registers ( 48h and 49h ) section. Modified Figure 4-3 . Added note to Table 4-8 , Alarm Threshold Registers. Changes to description of Thermal Management . Modified Figure 5-1 . Updated Conversion Phase and Event-Driven Sampling . Added to description of Acquisition Phase . Updated External Analog Inputs . Modified Figure 6-3 . Modified Example Design Instantiation and Example Design Test Bench . Updated Using XADC Instantiation Wizard . Updated Figure 6-7 .



Updated link to UG585 in References .



Updated Figure 1-2 , Figure 2-10 , and Figure 3-3 . Updated V REFP_0 package pin description in Table 1-1 . Updated Gain Coefficients and Single Pass Mode . Added second paragraph to Chapter 4, XADC Operating Modes introduction.



Clarified 7 series terminology throughout. Updated Preface to include Zynq-7000 SoC description, and added link to design files. Modified location of ferrite beads in Figure 1-2 and Figure 6-1 . Added equation and explanation to XADC DRP JTAG Write Operation in Chapter 3 . Modified Thermal Management in Chapter 4 , including adding three equations and Figure 4-4 . Added Vivado design tools information to XADC Enhanced Linearity Mode . Added settling period information to Event-Driven Sampling . Updated Figure 5-2 and removed timing information from Figure 5-3 . Updated Figure 6-7 .



Updated Over and Under Voltages .



Made typographical edits.



Updated Reference Inputs (V REFP and V REFN ) and External Analog Inputs .



Updated External Analog Inputs and Auxiliary Analog Inputs . Changed INIT_53 in examples to 125°C with automatic shutdown. Updated V CCO_DDR address in Table 4-3 . Updated Equation 4-1 and Equation 4-3 . Standardized figure format.



Added Spartan-7 devices throughout.

Updated introductory paragraph in About This Guide . Added DS180 to References .



Added a second note to Table 3-12 . Standardized figure format.



Typographical updates.



Revised DI and DADDR direction in Figure 1-3 . Changed bit DI3 to DI4 in Table 3-4 . Added constraint information to second paragraph in Thermal Management .