Continuous Sampling

7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

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Continuous Sampling

In continuous sampling mode, the ADCs continue to carry out a conversion on the selected analog inputs. Figure 5-1 shows the timing associated with continuous sampling mode. The ADCCLK is generated by a clock divider. The analog-to-digital conversion process is made up of two parts, the acquisition phase and the conversion phase.

Figure 5-1: Continuous Sampling Mode

X-Ref Target - Figure 5-1


Acquisition Phase

During the acquisition phase, the ADC acquires the voltage on a selected channel to perform the conversion. The acquisition phase involves charging a capacitor in the ADC to the voltage on the selected channel (see Analog Input Description, page 23 for more information). The time required to charge this capacitor depends on the selected input-channel source impedance. The XADC allows the acquisition of the next channel to start during the current conversion. This is possible because the ADC has a separate track-and-hold amplifier (T/H). Thus, when the ADC starts to convert an input voltage, the T/H is free to start precharging to the next voltage to be converted. This allows for a faster sampling rate because the ADC does not need to acquire the full input voltage at the end of the current conversion. By default, a settling period of four ADCCLK cycles is left between the end of the current conversion and the start of the next conversion. This can be extended to 10 ADCCLK cycles by setting the ACQ bits in either the control registers (single channel mode) or the sequence registers (sequencer modes). The additional ADCCLK cycles are useful when the external channel has a large source impedance (greater than 10 k ).

When operating in single channel mode (see Chapter 4, XADC Operating Modes ), you must write to configuration register 0 to select the next channel for conversion. The address of the next channel to convert is read from the control registers at the end of the previous conversion (when BUSY goes Low), and the analog signal is acquired during the current conversion. Additional acquisition or settling time after the end of the current conversion is configured by the ACQ bit in configuration register 0.

For more information on the effects of source impedance on the acquisition, see Analog Input Description .

Conversion Phase

The conversion phase starts on the sampling edge (next rising edge of DCLK) at the end of the 4 or 10 ADCCLK cycles settling time. The BUSY signal transitions to an active-High on the next rising edge of DCLK to indicate the ADC is carrying out a conversion. The conversion phase is 22 ADCCLK cycles long. 16 DCLK cycles after BUSY goes Low, EOC pulses High for one DCLK cycle when the conversion results have been transferred to the output registers. EOS indicates the end of a sequence, which depends on the automatic channel sequencer settings and averaging settings. If the automatic channel sequencer is used, then EOS matches the last channel enabled (see Table 4-1 ). When averaging is used, EOS only pulses High after all the samples have been completed (16, 64, and 256). The number of samples is set by AVG0 and AVG1 in Configuration Reg #0 ( 40h ) (see Table 3-8 ).

When XADC is being operated in a sequence mode, you can identify the channel being converted by monitoring the channel address (CHANNEL[4:0]) logic outputs. The multiplexer channel address of the channel being converted is updated on these logic outputs when BUSY transitions Low at the end of the conversion phase. The channel address outputs can be used with the EOC and DRDY signals to automatically latch the contents of the output data registers into a FIFO or block RAM. This is accomplished by connecting the CHANNEL[4:0] outputs to DADDR[4:0] (with DADDR[6:5] = 0), using EOC as a DEN (enable) for the DRP, and using DRDY as a WE (write enable) for the block RAM.

XADC EOS signal has the same timing as EOC. This signal is pulsed when the output data register for the last channel in a programmed channel sequence is updated.