Status Registers

The first 64 address locations (DADDR[6:0] = 00h to 3Fh ) contain the read-only status registers. The status registers contain the results of an analog-to-digital conversion of the on-chip sensors and external analog channels. All sensors and external analog-input channels have a unique channel address (see Table 3-7, page 38 ). The measurement result from each channel is stored in a status register with the same address on the DRP.

For example, the result from an analog-to-digital conversion on ADC multiplexer channel 0 (temperature sensor) is stored in the status register at address 00h . The result from ADC multiplexer channel 1 (V _CCINT ) is stored at address 01h .

The status registers also store the maximum and minimum measurements recorded for the on-chip sensors from the device power-up or the last user reset of the XADC. Table 3-1 defines the status registers.

Table 3-1: Status Registers (Read Only)
Name	Address	Description
Temperature	00h	The result of the on-chip temperature sensor measurement is stored in this location. The data is MSB justified in the 16-bit register. The 12 MSBs correspond to the temperature sensor transfer function shown in Figure 2-9, page 26 .
V _CCINT	01h	The result of the on-chip V _CCINT supply monitor measurement is stored at this location. The data is MSB justified in the 16-bit register. The 12 MSBs correspond to the supply sensor transfer function shown in Figure 2-10, page 27 .
V _CCAUX	02h	The result of the on-chip V _CCAUX data supply monitor measurement is stored at this location. The data is MSB justified in the 16 bit register. The 12 MSBs correspond to the supply sensor transfer function shown in Figure 2-10 .
V _P /V _N	03h	The result of a conversion on the dedicated analog input channel is stored in this register. The data is MSB justified in the 16-bit register. The 12 MSBs correspond to the transfer function shown in Figure 2-6, page 24 or Figure 2-7, page 24 depending on analog input mode settings.
V _REFP	04h	The result of a conversion on the reference input V _REFP is stored in this register. The 12 MSBs correspond to the ADC transfer function shown in Figure 2-10 . The data is MSB justified in the 16-bit register. The supply sensor is used when measuring V _REFP .
V _REFN	05h	The result of a conversion on the reference input V _REFN is stored in this register. This channel is measured in bipolar mode with a two's complement output coding as shown in Figure 2-3, page 20 . By measuring in bipolar mode, small positive and negative offset around 0V (V _REFN ) can be measured. The supply sensor is also used to measure V _REFN , thus 1 LSB = 3V/4096. The data is MSB justified in the 16-bit register.
V _CCBRAM	06h	The result of the on-chip V _CCBRAM supply monitor measurement is stored at this location. The data is MSB justified in the 16-bit register. The 12 MSBs correspond to the supply sensor transfer function shown in Figure 2-10 .
Undefined	07h	This location is unused and contains invalid data.
Supply A offset	08h	The calibration coefficient for the supply sensor offset using ADC A is stored at this location.
ADC A offset	09h	The calibration coefficient for the ADC A offset is stored at this location.
ADC A gain	0Ah	The calibration coefficient for the ADC A gain error is stored at this location.
Undefined	0Bh to 0Ch	These locations are unused and contain invalid data.
V _CCPINT ⁽¹⁾	0Dh	The result of a conversion on the PS supply, V _CCPINT is stored in this register. The 12 MSBs correspond to the ADC transfer function shown in Figure 2-10, page 27 . The data is MSB justified in the 16-bit register. The supply sensor is used when measuring V _CCPINT .
V _CCPAUX ⁽¹⁾	0Eh	The result of a conversion on the PS supply, V _CCPAUX is stored in this register. The 12 MSBs correspond to the ADC transfer function shown in Figure 2-10, page 27 . The data is MSB justified in the 16-bit register. The supply sensor is used when measuring V _CCPAUX .
V _{CCO_DDR} ⁽¹⁾	0Fh	The result of a conversion on the PS supply, V _{CCO_DDR} is stored in this register. The 12 MSBs correspond to the ADC transfer function shown in Figure 2-10, page 27 . The data is MSB justified in the 16-bit register. The supply sensor is used when measuring V _{CCO_DDR} .
VAUXP[15:0]/ VAUXN[15:0]	10h to 1Fh	The results of the conversions on auxiliary analog input channels are stored in this register. The data is MSB justified in the 16-bit register. The 12 MSBs correspond to the transfer function shown in Figure 2-2, page 19 or Figure 2-3, page 20 depending on analog input mode settings.
Max temp	20h	Maximum temperature measurement recorded since power-up or the last XADC reset.
Max V _CCINT	21h	Maximum V _CCINT measurement recorded since power-up or the last XADC reset.
Max V _CCAUX	22h	Maximum V _CCAUX measurement recorded since power-up or the last XADC reset.
Max V _CCBRAM	23h	Maximum V _CCBRAM measurement recorded since power-up or the last XADC reset.
Min temp	24h	Minimum temperature measurement recorded since power-up or the last XADC reset.
Min V _CCINT	25h	Minimum V _CCINT measurement recorded since power-up or the last XADC reset.
Min V _CCAUX	26h	Minimum V _CCAUX measurement recorded since power-up or the last XADC reset.
Min V _CCBRAM	27h	Minimum V _CCBRAM measurement recorded since power-up or the last XADC reset.
V _CCPINT ⁽¹⁾ max	28h	Maximum V _CCPINT measurement recorded since power-up or the last XADC reset.
V _CCPAUX ⁽¹⁾ max	29h	Maximum V _CCPAUX measurement recorded since power-up or the last XADC reset.
V _{CCO_DDR} ⁽¹⁾ max	2Ah	Maximum V _{CCO_DDR} measurement recorded since power-up or the last XADC reset.
Unassigned	2Bh
V _CCPINT ⁽¹⁾ min	2Ch	Minimum V _CCPINT measurement recorded since power-up or the last XADC reset.
V _CCPAUX ⁽¹⁾ min	2Dh	Minimum V _CCAUX measurement recorded since power-up or the last XADC reset.
V _{CCO_DDR} ⁽¹⁾ min	2Eh	Minimum V _{CCO_DDR} measurement recorded since power-up or the last XADC reset.
Unassigned	2Fh
Supply B offset	30h	The calibration coefficient for the supply sensor offset using ADC B is stored at this location.
ADC B offset	31h	The calibration coefficient for the ADC B offset is stored at this location.
ADC B gain	32h	The calibration coefficient for the ADC B gain error is stored at this location.
Undefined	33h to 3Eh	These locations are unused and contain invalid data.
Flag	3Fh	This register contains general status information (see Flag Register ).
Notes: 1. These channels are only available in Zynq-7000 SoC devices.

Flag Register

The Flag Register is shown in Figure 3-2 . The bit definitions are described in Table 3-2 .

Figure 3-2: Flag Registers
X-Ref Target - Figure 3-2

Table 3-2: Flag Register Bit Definitions
Bit	Name	Description
DI7 to DI0	ALM6 to ALM0	These bits reflect the status of the alarm output ALM[6:0].
DI3	OT	This bit reflects the status of the over temperature logic output.
DI9	REF	When this bit is a logic 1, the ADC is using the internal voltage reference. When this bit is a logic 0, the external reference is being used.
DI10	JTGR	A logic 1 indicates that the JTAG_XADC bitstream option has been used to restrict JTAG access to read only. See DRP JTAG Interface for more information.
DI11	JTGD	A logic 1 indicates that the JTAG_XADC bitstream option has been used to disable all JTAG access. See DRP JTAG Interface for more information.

XADC Calibration Coefficients

The XADC can digitally calibrate out any offset and gain errors in the ADCs and power supply sensor. By connecting known voltages (for example, V _REFP and V _REFN as opposed to the internal reference) to the ADCs and the supply sensor, the offset and gain errors can be calculated and correction coefficients generated. These calibration coefficients are stored in status registers 08h to 0Ah for ADC A and 30h to 32h for ADC B (see Table 3-1, page 30 ).

The XADC has a built-in calibration function that automatically calculates these coefficients. By initiating a conversion on channel 8 ( 08h ), all calibration coefficients are calculated. The XADC default operating mode automatically uses calibration. When not operating in the default mode, these calibration coefficients are applied to all ADC measurements by enabling the calibration bits (CAL0–3) in configuration register 1 ( 41h ) (see Table 3-5, page 37 ).

BUSY transitions High for the duration of the entire calibration sequence (conversion on channel 8). This calibration sequence is four times longer than a regular conversion on a sensor channel as offset and gain are measured for both ADCs and the power supply sensor.

Calibration Coefficients Definition

As mentioned previously, the offset and gain calibration coefficients are stored in the status registers. This section explains how to interpret the values in these registers. These are read-only registers, and it is not possible to modify the contents through the DRP. See Figure 3-3 .

Figure 3-3: Calibration Coefficients in Status Register
X-Ref Target - Figure 3-3

Note: The ADCs always produce a 16-bit conversion result. The 12-bit data correspond to the 12 MSBs (most significant) in the 16-bit status registers. The unreferenced LSBs can be used to minimize quantization effects or improve resolution through averaging or filtering.

Offset Coefficients

The offset calibration registers store the offset correction factor for the supply sensor and ADC. The offset correction factor is a 12-bit, two’s complement number and is expressed in LSBs. Similar to other status registers, the 12-bit values are MSB justified in the registers. For example, if the ADC has an offset of +10 LSBs (approximately 10 x 250 µV = 2.5 mV), the offset coefficient records –10 LSBs or FF6h , and status register 08h records 1111 , 1111 , 1100 XXXXb . For the supply sensor, the LSB size is approximately 750 µ V, thus a +10 LSB offset is equivalent to 7.5 mV of offset in the supply measurement.

Gain Coefficients

The ADC gain calibration coefficient stores the correction factor for any gain error in the ADCs. The correction factor is stored in the seven LSBs of registers 0Ah and 32h . These seven bits store both sign and magnitude information for the gain correction factor. If the seventh bit is a logic 1, the correction factor is positive. If it is 0, the correction factor is negative. The next six bits store the magnitude of the gain correction factor. Each bit is equivalent to 0.1%.

For example, if the ADC A has a positive gain error of +1%, then the gain calibration coefficient records –1% (the –1% correction applied to cancel the +1% error). Because the correction factor is negative, the seventh bit is set to zero. The remaining magnitude bits record 1%, where 1% = 10 x 0.1% and 10 = 001010 binary. The status register 0Ah records 0000 0000 0000 1010 . With six bits assigned to the magnitude and a maximum value of 3Fh , the calibration can correct errors in the range of ± 0.1% x 63, or 6.3%.