Table 1. Package Details (All Dimensions in mm)
| Package |
Size |
I/O |
Pitch |
Ball/ Column Size |
Pad Opening |
Pad Type |
Die Size |
Substrate |
| FFVB2104 |
47.5 x 47.5 |
2104 |
1.00 |
0.60 |
0.53 |
SMD |
18 x 22.5 x 0.762 |
1.42 thick, 14-layer |
Mother Board Design and Assembly Details
- 28-layer, Megtron-6, 290 x 140 x 3.4 mm size, OSP finish
- 0.53 mm pad diameter/0.63 mm solder mask opening (NSMD pads)
- Board layer structure: 28 layer with simulated power, ground (70% metal), and signal (40% metal) layer
- 0.127 mm laser cut stencil, 0.530 mm aperture, Indium 8.9HF paste
Test Condition
- 0°C–100°C, 40-minute thermal cycle, 10-minute dwells, 10°C/minute ramp rate
Failure Criteria
- Continuous scanning of daisy chain nets with event detector
- FAIL: Resistance of net > threshold resistance (500Ω), 10 events (maximum), 1 μs duration (maximum)
Table 2. Summary of Test Results
| Package |
Cycles Completed |
Number Tested |
Number Failed |
First Failure (Cycle) |
Characteristic Life (Cycle) |
| FFVB2104 |
8568 |
32 |
14 |
5205 |
9351 |
Weibull Plots
Figure 1. Cycles to Failure in the Second-Level Reliability Tests for
FFVB2104
