Temperature Cycling Test - Temperature Cycling Test - UG116

Device Reliability Report (UG116)
Document ID
UG116
Release Date
2025-07-23
Revision
10.20 English

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.

Summary

Table 1. Summary of Temperature Cycling Test Results
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3Sxxx TCB 5 0 215 255,000
XC3SxxxE TCB 11 0 465 667,500
XC5VxXxxx TCB 4 0 180 225,000
XC6Sxxx TCB 6 0 265 437,400
XC6VxXxxx TCB 4 0 178 222,000
7 series FPGAs and Zynq 7000 SoCs TCB 12 0 529 884,000
UltraScale devices TCB 10 0 450 562,500
UltraScale+ devices TCB, TCG 24 0 1,039 1,663,000
Versal devices TCB, TCG, TCK 13 0 458 569,000

Data

Table 2. TC Test Results for XC3Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1000 TCB 5 0 215 255,000
XC3Sxxx TCB 5 0 215 255,000
Table 3. TC Test Results for XC3SxxxE
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1200E TCB 3 0 120 240,000
XC3S250E TCB 4 0 170 210,000
XC3S500E TCB 4 0 175 217,500
XC3SxxxE TCB 11 0 465 667,500
Table 4. TC Test Results for XC5VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC5VLX110T TCB 4 0 180 225,000
XC5VxXxxx TCB 4 0 180 225,000
Table 5. TC Test Results for XC6Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6SLX150T TCB 2 0 105 117,400
XC6SLX45 TCB 4 0 160 320,000
XC6Sxxx TCB 6 0 265 437,400
Table 6. TC Test Results for XC6VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6VLX240T TCB 4 0 178 222,000
XC6VxXxxx TCB 4 0 178 222,000
Table 7. TC Test Results for 7 series FPGAs and Zynq 7000 SoCs
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC7A100T TCB 4 0 170 210,000
XC7Z020 TCB 8 0 359 674,000
7 series FPGAs and Zynq 7000 SoCs TCB 12 0 529 884,000
Table 8. TC Test Results for UltraScale Devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCKU040 TCB 7 0 315 405,000
XCVU095 TCB 3 0 135 157,500
UltraScale devices TCB 10 0 450 562,500
Table 9. TC Test Results for UltraScale+ Devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVU13P TCG 7 0 314 403,500
XCVU19P TCG 2 0 50 67,500
XCZU19EG TCB 1 0 45 67,500
XCZU3EG TCB 8 0 359 718,000
XCZU9EG TCB 6 0 271 406,500
UltraScale+ devices TCB, TCG 24 0 1,039 1,663,000
Table 10. TC Test Results for Versal Devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVC1702 TCB 1 0 45 67,500
XCVC1902 TCB 5 0 219 307,500
XCVH1542 TCG 2 0 54 54,000
XCVP1702 TCG 1 0 30 30,000
XCVP1802 TCG 1 0 30 30,000
XCVP2802 TCG 3 0 80 80,000
Versal devices TCB, TCG, TCK 13 0 458 569,000