Temperature Cycling Test - UG116

Device Reliability Report (UG116)
Document ID
UG116
Release Date
2024-11-08
Revision
10.19 English

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.

Summary

Table 1. Summary of Temperature Cycling Test Results
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3Sxxx TCB 3 0 120 180,000
XC3SxxxE TCB 6 0 236 392,000
XC5VxXxxx TCB 2 0 90 135,000
XC6Sxxx TCB 2 0 80 160,000
XC6VxXxxx TCB 2 0 89 133,500
7 series FPGAs and Zynq 7000 SoCs TCB 6 0 239 438,000
UltraScale devices TCB 6 0 267 378,000
UltraScale+ devices TCB, TCG 16 0 715 1,117,500
Versal devices TCB, TCG, TCK 41 0 958 1,063,500

Data

Table 2. TC Test Results for XC3Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1000 TCB 3 0 120 180,000
XC3Sxxx TCB 3 0 120 180,000
Table 3. TC Test Results for XC3SxxxE
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1200E TCB 2 0 76 152,000
XC3S250E TCB 2 0 80 120,000
XC3S500E TCB 2 0 80 120,000
XC3SxxxE TCB 6 0 236 392,000
Table 4. TC Test Results for XC5VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC5VLX110T TCB 2 0 90 135,000
XC5VxXxxx TCB 2 0 90 135,000
Table 5. TC Test Results for XC6Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6SLX45 TCB 2 0 80 160,000
XC6Sxxx TCB 2 0 80 160,000
Table 6. TC Test Results for XC6VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6VLX240T TCB 2 0 89 133,500
XC6VxXxxx TCB 2 0 89 133,500
Table 7. TC Test Results for 7 Series FPGAs and Zynq 7000 SoCs
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC7A100T TCB 2 0 80 120,000
XC7Z020 TCB 4 0 159 318,000
7 series FPGAs and Zynq 7000 SoCs TCB 6 0 239 438,000
Table 8. TC Test Results for UltraScale devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCKU040 TCB 3 0 134 201,000
XCKU060 TCB 1 0 45 67,500
XCVU095 TCB 2 0 88 109,500
UltraScale devices TCB 6 0 267 378,000
Table 9. TC Test Results for UltraScale+ devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVU13P TCG 5 0 223 289,500
XCZU15EG TCB 1 0 45 67,500
XCZU27DR TCB 1 0 44 66,000
XCZU3EG TCB 5 0 225 450,000
XCZU9EG TCB 4 0 178 244,500
UltraScale+ devices TCB, TCG 16 0 715 1,117,500
Table 10. TC Test Results for Versal devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVC1702 TCB 6 0 96 96,000
XCVC1902 TCB 4 0 172 245,100
XCVH1542 TCG 4 0 108 108,000
XCVM1402 TCB 10 0 140 140,000
XCVP1202 TCB 6 0 142 142,000
XCVP1702 TCG 3 0 84 94,800
XCVP1802 TCG 4 0 109 109,000
XCVP1902 TCK 1 0 27 48,600
XCVP2802 TCG 3 0 80 80,000
Versal devices TCB, TCG, TCK 41 0 958 1,063,500