Reliability Monitor Program

Device Reliability Report (UG116)

Document ID
Release Date
10.17 English

The wafer process reliability monitor program is based on the maturity of the wafer process, the number of device hours, and the failure in time (FIT) rate. All processes are divided into one of two classes to determine how often the process is monitored annually. Class 1 processes are monitored every quarter; Class 2 processes are monitored every other quarter. FIT Rate calculations for both classes are based on approximately one million device hours (at TJ = 125°C) per fab if the data is available. Processes that are four years old or less are monitored every quarter regardless of the FIT rate. Mature processes older than four years are monitored based on the FIT Rate. The following table summarizes the classification criteria and monitoring frequency for both classes.

Table 1. Monitoring Process Classes
  Class 1 Class 2
Classification Criteria

Process Age  4 years


FIT > 26 (for FPGAs), 55 (for Flash PROM)

Process Age > 4 years


FIT < 26 (for FPGAs), 55 for Flash PROMs)

Monitor Frequency 4 times per year 2 times per year

The following table shows the reliability tests used to monitor the wafer process.

Table 2. Tests Used to Monitor Wafer Processes
Reliability Test Condition Duration Lot Quantity Sample Size per Process per Family per Quarter
HTOL Tj > 125°C, VDD Max 1,000 hours 1 45
Data Retention Bake 1 TA = 150°C 1,000 hours 1 45
  1. For CPLD and PROM products.

The package reliability monitor program takes into consideration the following factors:

  • Package construction (wire-bond lead frame, wire-bond BGA, or flip chip)
  • Factory location (assembly site, or wafer fabrication site)
  • Substrate vendor
  • Die size
  • Technology maturity
  • Past history

Based on these factors and availability, representative packages are drawn from inventory for the stress tests defined in the following table. These tests are typically conducted on a quarterly basis, but the number of tests can be reduced or eliminated based on the maturity of the package technology, understanding of failure mechanisms, and their dependency on the stress test.

Table 3. Tests Used by the Reliability Package Monitor Program
Reliability Test Stress Conditions Stress Duration Sample Size Frequency
THB 1 or HAST 1 85°C, 85% RH, VDD 1,000 hrs 45 WBLF 2 every even quarter WBBGA 3 every odd quarter Flip Chip 4 every quarter
130°C, 85% RH, VDD 96 hrs
110°C, 85% RH, V DD 264 hrs
Temperature cycling 1, 5 –55°C to +125°C or –40°C to +125°C 1,000 cycles 45 WBLF every quarter WBBGA every quarter Flip Chip every quarter
Autoclave 1, 6 or Temperature humidity unbiased 1, 6 or UHAST 1, 6 121°C, 100% RH 96 hrs 45 WBLF every odd quarter WBBGA every even quarter
85°C, 85% RH 1,000 hrs
130°C, 85% RH or 110°C, 85% RH 96 hrs or 264 hrs
HTS TA=150°C 1,000 hrs 45 WBLF every quarter WBBGA every quarter
  1. Package preconditioning is performed prior to THB, HAST, temperature cycling, autoclave, TH, and UHAST tests.
  2. For matured WBLF packages (PLCCs, SOICs, and DIPs packages), reliability monitoring is performed once a year.
  3. For matured WBBGA packages (S-BGA Cavity-down BGA), reliability monitoring is performed once a year.
  4. For flip chip packages, THB testing is performed every quarter and replaces the need for temperature humidity testing.
  5. For plastic QFP and BGA packages: –55°C to +125°C and 1,000 cycles; for flip chip packages: –55°C to +125°C and 1,000 cycles or 40°C/+125°C and 1,000 cycles.
  6. Refer to the device-specific qualification report for complete autoclave, temperature humidity, and UHAST reliability test data.