The Vitis unified IDE provides examples to get started. Click Examples in the Welcome page which allows you to choose from a list of examples available under AI Engine Examples section as shown below.
Figure 1.
AI Engine
Examples
The AI Engine Examples illustrate the basic features of AI Engine programming. You can study these examples, use them as a starting point for your own projects, or mix and match the features to create your own complex computation graphs. The following table describes some of the templates.
| Template Name | Description | Further Information |
|---|---|---|
| AI Engine, PL and PS System Design | This design demonstrates integrating the AI Engine array with the Programmable Logic and the Processing System in a system. It performs hardware co-simulation and hardware implementation. | Building and Running the System in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) |
| Async Buffer | A graph to demonstrate asynchronous window APIs. | Asynchronous Buffer Port Access in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Async RTP Control Iterative | A graph to demonstrate simple use of asynchronous RTP update and run with specified test iterations. | Graph Execution Control in AI Engine Kernel and Graph Programming Guide (UG1079). |
| C++ template example | An example demonstrating C++ templated data types and state encapsulation. | C++ Template Support in AI Engine Kernel and Graph Programming Guide (UG1079). |
| GMIO Bandwidth | A graph to demonstrate GMIO performance profiling. | Configuring input_gmio/output_gmio in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Mapping Placement | A templated graph with relocatable mapping and location constraints for kernels. | Location Constraints in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Shim Constraints | A graph to demonstrate physical channel allocation constraints on the AI Engine to PL interface boundary. | AI Engine/Programmable Logic Integration in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple | A simple 2-kernel graph with window based data communication. | Buffer Port-Based Access in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple 128 Bit Interface | A graph to demonstrate 128-bit interface between the AI Engine and PL. | Configuring input_plio/output_plio in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple 64 Bit Interface | A graph to demonstrate 64-bit interface between the AI Engine and PL. | Configuring input_plio/output_plio in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple Bypass | A graph demonstrating the use of bypass for kernels. | Kernel Bypass in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple Margin | A graph demonstrating the use of margin in windows (overlapping windows). | Buffer Port-Based Access in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple Packet Split Merge | A graph to demonstrate simple split and merge of packet stream data. | Explicit Packet Switching in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple Param | A simple 1-kernel graph with scalar parameter update using external trigger. | Specifying Run-Time Data Parameters in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Simple Single Buffer | A graph demonstrating single buffer constraint on connections. | Buffer Allocation Control in AI Engine Kernel and Graph Programming Guide (UG1079). |
| Single Node Graph | A simple single node graph with demonstration window (single buffer and double buffer), stream and RTP array connections. | Single Kernel Development |
| Stream Switch FIFO | A graph to demonstrate use of stream switch FIFO to avoid deadlocks with reconvergent streams. | FIFO Depth in AI Engine Kernel and Graph Programming Guide (UG1079). |