Evaluate FIFO Depth To Break Deadlocks - 2023.2 English

AI Engine Tools and Flows User Guide (UG1076)

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2023.2 English

When your system is deadlocked, adding FIFOs within the design might help. In a simple system, you can infer the FIFO sizes from the design and do a manual static analysis. However, you do not know exactly how many clock cycles are spent in the main_init(), the main(), and the beginning of your kernel.

The tool computes these FIFO lengths from an AI Engine simulation for you. You can compile your graph with aiecompiler using the flag --evaluate-fifo-depth. This option generates infinite FIFOs on all relevant paths.

Once your code is compiled, run a standard AI Engine simulation with aiesimulator. Near the beginning of the simulation you will get this warning:
[CRITICAL WARNING]: Design was compiled with --evaluate-fifo-depth option, before deploying the design on hardware compile without --evaluate-fifo-depth option.
  1. Open Vitis Unified IDE and open the simulation run_summary.
  2. Note the Estimated FIFO column, and apply the recommended number of FIFOs using the fifo_depth constraint on specific nets.
Note: This feature is not available for AI Engine-ML designs.
Figure 1. Vitis Unified IDE
The estimated FIFO depth are given in the Estimated FIFO (Words) column. These values can be used in the graph to insert FIFOs with the specified length using the following syntax:
fifo_depth(net) = value;
Where net is a connection on which you want to insert a FIFO.