To simulate the entire system, including AI Engine graph and PL logic along with XRT-based host application to control the AI Engine and PL, for a specific board and platform, you must use the Vitis hardware emulation flow. This flow includes the SystemC model of the AI Engine, transaction-level SystemC models for the NoC, DDR memory, PL Kernels (RTL), and PS (running on QEMU). You can also include RTL logic and test bench PL logic for your platform or design. Details on the flow can be found in Speed and Accuracy of Hardware Emulation in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
For details on speed and accuracy of the system including AI Engine, PL models, NoC, DDR memory, PS and other I/O models, please see link.
Scope of HW Emulation is limited to modeling only functional performance of PS-to-AIE communication. Tests that rely on PS-AIE latency, that include features such as asynchronous RTP, where PS updates are propagated asynchronously, or tests that involve PS-initiated DDR activities, may be impacted by the reduced accuracy.