These documents provide supplemental material useful
with this guide:
- The AI Engine Intrinsics User Guide (UG1078)
- AI Engine-ML Intrinsics User Guide (UG1583)
- AI Engine Kernel and Graph Programming Guide (UG1079)
- AI Engine-ML Kernel and Graph Programming Guide (UG1603)
- Data Center Acceleration using Vitis (UG1700)
- Embedded Design Development Using Vitis (UG1701)
- Vitis Reference Guide (UG1702)
- Vitis Software Platform Release Notes (UG1742)
- Versal Adaptive SoC AI Engine Architecture Manual (AM009)
- Versal Adaptive SoC Register Reference (AM012)
- Versal Adaptive SoC AI Engine Register Reference (AM015)
- Versal Adaptive SoC AIE-ML Architecture Manual (AM020)
- Versal Adaptive SoC AIE-ML Register Reference (AM025)
- The ASIP Programmer Chess Compiler User Manual, found on the Versal AI Engines Secure Site, provides a list of all the pragmas and functions to help optimize your AI Engine kernel code.
- AI Engine API User Guide (UG1529)
- Vitis Model Composer User Guide (UG1483)
- SmartLynq+ Module User Guide (UG1514)
- Versal adaptive SoC data sheets:
- Versal Adaptive SoC Design Guide (UG1273)
- Power Design Manager User Guide (UG1556)
- Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
- Answer Records:
- AI Engine Compiler - General Guidance and Known Issues for the Vitis 2020.2 tool and later versions (Answer 75790)
- AIE Simulator - General Guidance and Known Issues for the Vitis 2020.2 tool and later versions (Answer 75788)
- AI Engine Solution Center (Answer 75837)