The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/30/2024 Version 2.0 | |
| VTC Registers | Updated the section. |
| Clocking | Updated the table. |
| S_AXIS_STS_SB_TX Interface Signals | Updated the table. |
| 05/16/2023 Version 2.0 | |
| Versal Adaptive SoC Block Automation in UHD-SDI TX Subsystems | Updated the section. |
| 10/19/2022 Version 2.0 | |
| Unsupported Features, Native SDI Signals, Native Video (VID_IO_IN) Interface Signals | Updated the sections. |
| 05/18/2022 Version 2.0 | |
| N/A | Editorial changes. |
| 04/26/2022 Version 2.0 | |
| N/A |
Added parameters to select HFR and YCbCr444 support to reduce resource count. |
| 06/30/2021 Version 2.0 | |
| N/A |
Added HFR Support for 10-bit 6G/12G mode at AXI Interface Subsystem Level |
| Unsupported Features | Updated the section. |
| N/A | Updated module control register description for HFR. |
| PICXO FRACXO IP Core | Added for PICXO. |
| 01/11/2021 Version 2.0 | |
| N/A | Added Versal Adaptive SoC support. |
| Versal Adaptive SoC Block Automation in UHD-SDI TX Subsystems | Added the section. |
| Programming Sequence | Added the section. |
| Unsupported Features | Updated the section. |
| Compiling Software in the Vitis Software Platform | Updated the section. |
| 11/18/2020 Version 2.0 | |
| IP Facts | Added Support for HLG HDR. |
| 09/15/2020 Version 2.0 | |
| N/A | Updated 12-bit and HFR support in the following sections: |
| Example Design | Updated the Clocking section. |
| Designing with the Subsystem | Updated the Clocking section. |
| CPLL Clocking | Added information on CPLL-QPLL usage for 12G SDI. |
| 06/14/2019 Version 2.0 | |
| Example Design Transceiver Configuration | Updated the figure. |
| 12/05/2018 Version 2.0 | |
| N/A | SMPTE 352: Payload packet insertion of Y stream and C stream supported |
| Application Example Design Tab | Added the section. |
| ZCU106 UHD-SDI Pass-Through with PICXO Example Design | Example Design added. |
| PICXO FRACXO IP Core | Added the section. |
| 04/04/2018 Version 2.0 | |
| N/A |
|
| 10/04/2017 Version 1.0 | |
| N/A | Initial Xilinx release. |