Resets - 2.0 English - PG289

SMPTE UHD- Transmitter Subsystem LogiCORE IP Product Guide (PG289)
Document ID
PG289
Release Date
2024-12-11
Version
2.0 English

The subsystem has three reset ports:

s_axi_arstn
Active-Low reset for the AXI4-Lite register interface and synchronous with s_axi_aclk.
video_in_arstn
Active-Low reset for the subsystem blocks and synchronous with video_in_clk.
sdi_tx_rst
Active-High reset for the SMPTE UHD-SDI TX core and synchronous with sdi_tx_clk. See the Clocking section the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205).

The following table summarizes all resets available to the SMPTE UHD-SDI TX Subsystem and the components affected by them.

Table 1. Core Resets
Sub-Core s_axi_arstn video_in_arstn sdi_tx_rst
AXI4-Stream to Video Out N/A N/A NA
Video to SDI TX Bridge N/A N/A Connected to rst core port
SMPTE UHD-SDI TX Connected to s_axi_aresetn core port Connected to axis_rstn core port Connected to tx_rst core port
Video Timing Controller Connected to s_axi_aresetn core port N/A N/A
AXI Crossbar Connected to aresetn core port N/A N/A
Note: The effect of each reset (s_axi_arstn, video_in_arstn, sdi_tx_rst) is determined by the ports of the sub-cores to which they are connected. See the individual sub-core product guides for the effect of each reset signal. All the resets should be active until the associated clocks are stable.