SDI_TX_BRIDGE_STS Register (0x68) - 2.0 English

SMPTE UHD-Transmitter Subsystem LogiCORE IP Product Guide (PG289)

Document ID
PG289
Release Date
2024-05-30
Version
2.0 English

This register is not updated when the native SDI interface is selected.

Table 1. SDI_TX_BRIDGE_STS Register Bit Mapping
Bits Name Access Default Value Description
31:7 Reserved RO 0 Reserved
6 BRIDGE_3G_LEVEL_B RO 0 Asserted High when incoming stream is 3G-SDI level B
5:4 3GBRIDGE_TX_MODE RO 0

3G Bridge TX mode

2’b00 : HD-SDI mode

2’b01 : SD-SDI mode

2’b10 : 3G-SDI mode

3:1 Reserved RO 0 Reserved
0 SDITX_BRIDGE_SEL RO 0

Select bits for SDI TX Bridge

0 – 3G SDI TX Bridge is selected

1 – 12G SDI TX Bridge is selected