These documents provide supplemental material useful with this guide:
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- SMPTE UHD-SDI LogiCORE IP Product Guide (PG205)
- AXI4-Stream to Video Out LogiCORE IP Product Guide (PG044)
- Video Timing Controller LogiCORE IP Product Guide (PG016)
- AXI4-Stream Video IP and System Design Guide (UG934)
- SMPTE UHD-SDI Receiver Subsystem Product Guide (PG290)
- Vivado Design Suite: AXI Reference Guide (UG1037)
- SmartConnect LogiCORE IP Product Guide (PG247)
- AXI Interconnect LogiCORE IP Product Guide (PG059)
- UHDSDI Audio LogiCORE IP Product Guide (PG309)
- UHD-SDI GT LogiCORE IP Product Guide (PG380)
- Versal Adaptive SoC GT Controller for DisplayPort and SDI (PG398)
- Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
- Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
- AMD GitHub
- AMD Wiki
- All Digital VCXO Replacement for Gigabit Transceiver Applications (UltraScale FPGAs) (XAPP1241)