Customizing and Generating the Core - 2.0 English

SMPTE UHD-Transmitter Subsystem LogiCORE IP Product Guide (PG289)
Document ID
PG289
Release Date
2024-05-30
Version
2.0 English

If you are customizing and generating the core in the AMD Vivado™ IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.

The following table describes the IP specifics:

Table 1. IP Facts Table
IP Specifics
Supported Device Family 1

AMD UltraScale+™ (GTHE4, GTYE4)

AMD Versal™ Adaptive SoC (GTYE5)

AMD Zynq™ UltraScale+™ MPSoC (GTHE4, GTYE4)

AMD Zynq™ UltraScale+™ RFSoC

Supported User Interfaces

AXI4-Lite, AXI4-Stream,

Native Video, Native SDI

Resources Performance and Resource Utilization web page
  1. For a complete list of supported devices, see the Vivado IP catalog.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

  1. Select the IP from the Vivado IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current version.

You can customize the core using the following parameters, or allow defaults to be used.