IP Facts - 2.0 English - PG289

SMPTE UHD- Transmitter Subsystem LogiCORE IP Product Guide (PG289)
Document ID
PG289
Release Date
2024-12-11
Version
2.0 English
AMD LogiCORE™ IP Facts Table
Subsystem Specifics
Supported Device Family 1

AMD UltraScale+™ (GTHE4, GTYE4)

AMD Versal™ Adaptive SoC (GTYE5, GTYP)

AMD Zynq™ UltraScale+™ MPSoC (GTHE4, GTYE4)

AMD Zynq™ UltraScale+™ RFSoC

Supported User Interfaces AXI4-Lite, AXI4-Stream, Native Video, Native SDI
Resources Performance and Resource Utilization web page
Provided with Subsystem
Design Files Hierarchical subsystem packaged with UHD-SDI TX IP core and other IP cores
Example Design AMD Vivado™ IP integrator
Test Bench N/A
Constraints File IP cores delivered with XDC files
Simulation Model N/A
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry AMD Vivado™ Design Suite
Simulation Not Supported
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 68767
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.

  2. Standalone driver details can be found in <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.

  3. For more information on the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).