Clock Frequency Selection - 2.0 English - PG289

SMPTE UHD- Transmitter Subsystem LogiCORE IP Product Guide (PG289)

Document ID
PG289
Release Date
2024-12-11
Version
2.0 English

The SMPTE UHD-SDI TX Subsystem inherently has multiple clock domains and has many CDC paths across the core. It is recommended to use maximum allowed clock frequency to reduce the uncertainty due to cdc paths.