The example design uses the UHD-SDI GT (uhdsdi_gt_v2_0) core to configure the AMD UltraScale+™ GTH transceivers and provides the option to select the transceiver reference clock. This core also generates control modules that are required to program the transceiver using the DRP interface.Figure 2 shows the AMD Vivado™ IDE configuration screen that is used in the ZCU106 application example design. See the UHD-SDI GT LogiCORE IP Product Guide (PG380) for information on this core.
Figure 1. (A) UHD-SDI GT Core Configuration
Figure 2. (B) UHD-SDI GT Core Configuration
