The demonstration test bench is defined in this file:
demo_tb.v
The demonstration test bench is a simple Verilog program that exercises the example design and the subsystem itself. The test bench has two modes of operation:
- DEMO
- Built-in Self Test (BIST)
BIST mode is the default.
The test bench consists of these component blocks:
- Clock generators
- DEMO (stimulus) – A stimulus block that connects to the PHY-side receiver interface of the example design (MII, GMII, RGMII, SFP or SGMII interfaces)
- DEMO (monitor) – A monitor block to check data returned through the PHY side transmitter interface
- DEMO – Basic frame filter that looks at the DA/SA fields of frame inserted into the PHY side receiver interface
- BIST – A simple loopback from the PHY side transmit interface to the receiver
- BIST (AVB only) – A basic AV data bandwidth monitor
- A management block to control the speed selection
- An MDIO monitor/stimulus block to check and respond to MDIO accesses