The transmit control block must maintain coherence between the data and control buses. Because data frames can vary from 1 byte to over 9 Kb in length and the control information for each frame is a constant six 32-bit words, care must be taken under conditions where the buffer for the frame data or control data fills up to prevent an out-of-sequence condition.
To maintain coherency, the AXI4-Stream data ready signal is held not ready until a AXI4-Stream control stream has been received. After this has occurred, the AXI4-Stream data ready signal is driven ready (as long as there is buffer space available) and the AXI4-Stream control ready signal is held not ready until the data stream transfer is complete (Refer to the following figure and Receive Status Transmit AXI4-Stream Transfer – Flag=0x5). The write strobe signals for the control and status buses are always in the active state (0xF).
The right-most write strobe signal for the data bus is always in the active state (0x1, 0x3, 0x7, or 0xF). These signals can be tied off rather than routing signals from the AXI4-Stream source to the destination. The AXI Ethernet Subsystem provides these ports to be compliant with the standard; however, there is not any logic based on these inputs which are considered constants. The transmit interface can encounter two AXI4-Stream transfer types: Normal Transmit or Receive Status Transmit, as described in the following sections.