Performance - 7.2 English - PG138

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2024-06-05
Version
7.2 English

To measure the system performance of the AXI Ethernet Subsystem, a system was built in which the subsystem was added to each of the supported device families as the Device Under Test (DUT) as shown in the following figure in which the subsystem serves as the DUT block.

Because the subsystem is used with other design modules in the FPGA, the utilization and timing numbers reported in this section are estimates. When this subsystem is combined with other designs in the system, the utilization of FPGA resources and timing of the subsystem design can vary from the results reported here.

Figure 1. System Configuration with the Subsystem as the DUT for All Supported Device Families AXI Ethernet Page-1 Rectangle.40 FPGA with example system FPGA with example system Rectangle.5 AXI Interrupt Controller AXI Interrupt Controller Rectangle.6 Memory Map Interconnect AXI4 Memory Map InterconnectAXI4 Rectangle.7 Peripheral Interconnect AXI4 Lite Peripheral InterconnectAXI4-Lite Rectangle Micro Blaze system Micro Blaze System Rectangle.3 MicroBlaze Controller MicroBlazeController Rectangle.3.3 BRAM Controller BRAMController Rectangle.4 MDM MDM Rectangle.10 AXI Memory Controller AXI Memory Controller Rectangle.11 AXI BRAM AXI BRAM Rectangle.12 AXI UART AXI UART Rectangle.13 AXI DMA AXI DMA Rectangle.14 AXI Ethernet AXI Ethernet Dynamic connector Dynamic connector.9 Dynamic connector.15 Dynamic connector.16 Dynamic connector.17 Dynamic connector.18 Dynamic connector.19 Dynamic connector.20 Dynamic connector.21 Dynamic connector.22 Dynamic connector.23 Dynamic connector.24 Dynamic connector.25 Dynamic connector.26 Dynamic connector.27 Dynamic connector.28 Sheet.30 IC IC Sheet.31 DC DC Sheet.32 DP DP Sheet.33 AXI lite interface AXI4-Lite Interface Sheet.34 AXI lite interface AXI4-Lite Interface Sheet.35 AXI Streaming Interfaces AXI4-Stream Interfaces Dynamic connector.35 Dynamic connector.36 Dynamic connector.37 Sheet.39 Ethernet interface Ethernet Interface Sheet.40 UART interface UART Interface Dynamic connector.41 Sheet.42 DDR Memory DDR Memory Sheet.43 X13253-030117 X13253-030117 Dynamic connector.44 Sheet.45 AXI Streaming Interfaces AXI4-Stream Interfaces

The target FPGA was then filled with logic to drive the LUT and block RAM utilization to approximately 70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target FPGA, the FTYP numbers are shown in the following table.

Table 1. System Performance FTYP
Target FPGA AXI4-Lite AXI4-Stream MicroBlaze™
Supported families 100 100 100

The target FMAX is influenced by the particular system. The FTYP typical use case frequency numbers are provided here.

Because the subsystem represents a hierarchical design block containing multiple IP instances, the latency, max frequency, throughput, and power values are provided by the IP instances that are present in a given configuration.