- HDL is generated for this hierarchical block.
- Examine this HDL for the I/O and interfaces generated. In many cases the required logic is generated automatically. Cross-check for the MDIO IOBUF instantiation as per the design requirement.
- Examine the address space that is allocated for the AXI Ethernet Subsystem in the IP integrator Address editor tab. The AXI Ethernet Subsystem requires a 256K address range.
- Examine the clocks required for the mode of operation and provide the clocks as required.
- If using a development board, check the board for the LOC constraints provided in the "Master Constraints" file delivered along with the board. Also check for the specific location constraints for transceivers.
- Synthesize and implement the entire design.
- After implementation is complete you can also create a bitstream that can be downloaded to an AMD device.