Resets - 7.2 English - PG138

The TEMAC components are reset using the following AXI4 reset signals: axi_str_txd_aresetn, axi_str_txc_aresetn, axi_str_rxd_aresetn, axi_str_rxs_aresetn, or s_axi_aresetn. All resets must pass through reset detection circuits that detect and synchronize the resets to the different clock domains.

As a result, any time the AXI Ethernet Subsystem is reset, sufficient time must elapse for a reset to propagate through the reset circuits and logic. The amount of time required is dependent upon the slowest AXI Ethernet clock. Allow 30 clock cycles of the slowest AXI Ethernet clock to elapse before accessing the subsystem. Failure to comply causes unpredictable behavior.

In a system in which Ethernet operates at 10 Mb/s, the Ethernet MAC interface operates at 2.5 MHz. If the AXI4-Lite interface operates at 100 MHz and the AXI4-Stream interface operates at 125 MHz, the time that must elapse before AXI Ethernet is accessed is 12 us (400 ns x 30 clock cycles).