The AXI Ethernet Subsystem requires that certain AXI4-Stream Control/Status words be used to support TCP/IP Checksum Offload. The
subsystem does not have any requirements on how the AXI4-Stream words are
created or where the data comes from, only that the correct values are in each field. At the
time that this document is written,AMD provides a core that can be used to
provide the require AXI4-Stream functionality to implement TCP / IP Checksum
Offload, the AXI_DMA IP core. See the change log for the version of AXI DMA to use.
The AXI DMA core is designed to operate with many AXI4-Stream cores in addition to the AXI Ethernet Subsystem. This guide contains
information about the mapping between the AXI Ethernet AXI4-Stream fields and
the AXI DMA Buffer Descriptor fields for the purposes of TCP / IP Checksum Offload.
The AXI DMA core uses registers to point to data areas in
external memory called Buffer Descriptors. The Buffer Descriptors are five 32-bit words in
external memory and contain AXI DMA operation control information, pointers to other areas of
external memory which contain data to move which are called Data Buffers, and generic
Application Defined words which map to AXI4-Stream Control and AXI4-Stream Status words.
The following first figure shows the mapping between the
AXI DMA Buffer Descriptor words in external memory and the fields in the transmit AXI4-Stream case and the second figure shows the mapping for the receive AXI4-Stream case. The first word in the AXI_STR_TXC_TDATA data contains the Flag
information that is directly set by the AXI DMA core, and the first word in the
AXI_STR_RXS_TDATA data contains the Flag information that is set by the AXI Ethernet
Subsystem.
Figure 1. Transmit AXI DMA Buffer Descriptor AXI4-Stream Field Mapping
Figure 2. Receive AXI DMA Buffer Descriptor AXI4-Stream Field Mapping