Received Timestamp Ports (Out-of-Band) - 7.2 English - PG138

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2024-06-05
Version
7.2 English

The captured timestamp will always be presented out-of-band with TEMAC frame reception using a dedicated AXI4-Stream interface. The signal definition for this is defined in the following table.

A timing diagram showing the operation of this interface follows the table. To summarize, the timestamp will be valid on the same clock cycle as the first data word of frame data. This AXI4-Stream interface is synchronous to the TEMAC receive clock.

Table 1. AXI4-Steam Interface Ports – Receive Timestamp
Name Direction Description
rx_ts_axis_tdata[127:0] Out

AXI4-Stream Receive Timestamp from the TEMAC.

Bits[127:80] - Reserved

Bits [79:32] - Captured Timestamp Seconds field

Bits [31:0] - Captured Timestamp Nano-seconds field

rx_ts_axis_tvalid Out AXI4-Stream Receive Timestamp Data Valid from the MAC
Figure 1. AXI4-Stream Interface Timing – Receive Timestamp AXI Ethernet Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 rx_mac_clk rx_mac_clk Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 rx_axis_tdata rx_axis_tdata Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 rx_axis_tvalid rx_axis_tvalid Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 rx_ts_axis_tdata[79:0] rx_ts_axis_tdata[79:0] Sheet.44 Sheet.45 Sheet.46 rx_axis_tlast rx_axis_tlast Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 rx_ts_axis_tvalid rx_ts_axis_tvalid Sheet.64 TS[79:0] TS[79:0] Sheet.65 X15633-100818 X15633-100818