For Kintex UltraScale KCU105 Board - 7.2 English

1. Do not use the phy_rst_n automation in SGMII over LVDS mode.

   Using this phy_rst_n causes a deadlock condition during reset. The on-board PHY of this board does not generate the reference clock during reset that is required by the AXI 1G/2.5G Ethernet subsystem to de-assert the phy_rst_n, thus causing a deadlock.

2. When using this board, select Include Shared Logic in IP Example Design for the AXI 1G/2.5G Ethernet subsystem.

The on-board PHY generates a 625 MHz clock. Using a clock wizard, the required clocks for this mode can be generated. Block automation also helps in connecting to a clock wizard. This mode also requires an IDELAY control module to be instantiated outside the AXI 1G/2.5G Ethernet subsystem.