When targeting a GMII design, a BUFGMUX is used to switch between the MII_TX_CLK and the GTX_CLK clocks. This allows the design to support data rates of 10/100 Mb/s and 1000 Mb/s. The FPGA pins for these clocks must be selected such that they are located in the same clock region and they are both on clock dedicated pins. The GMII status, control, and data pins must be chosen to be in the same clock region as these clocks. See the 7 Series FPGAs Clocking Resources User Guide (UG472) for the targeted FPGA family for more information.
In the Include Shared Logic in IP Example
Design configuration, the s_axi_lite_clk,
ref_clk, and axis_clk signals for the core are generated
from the *_clocks_resets module (within the example design) through an
MMCME3_ADV followed by BUFGs.
While using the core with GT in Example Design on Versal and UltraScale/UltraScale+ devices, the clocks are connected to the core from GT as follows.
| Clock | Description |
|---|---|
| userclk | Clock for the 16-bit TX data path
from the core to the GT. Frequency: 1G: 62.5 Mhz. 2.5G: 156.25 Mhz. |
| userclk2 | Clock for the 8-bit internal data
path within the PCS. Frequency: 1G: 125 Mhz. 2.5G: 312.5 Mhz. |
| rxuserclk | Not used |
| rxuserclk2 | Clock for the 16-bit RX data path from the GT to the core. Unused
in 1000/2500 BaseX modes where 1588 timestamping is disabled. The userclk is used when
rxuserclk2 is not used. Frequency: 1G: 62.5 Mhz. 2.5G: 156.25 Mhz. |