Ethernet GMII Interface - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The Ethernet GMII ports are described in the following table.

Table 1. Ethernet GMII Ports
Signal Name Direction Description
gmii_txd[7:0] Out TEMAC to PHY transmit data. Initial status 0.
gmii_tx_en Out TEMAC to PHY transmit enable. Initial status 0.
gmii_tx_er Out TEMAC to PHY transmit Error enable. Initial status 0.
gmii_gtx_clk Out TEMAC to PHY transmit clock. Initial status 0.
gmii_rxd[7:0] In PHY to TEMAC receive data.
gmii_rx_dv In PHY to TEMAC receive data valid indicator.
gmii_rx_er In PHY to TEMAC receive error indicator.
gmii_rx_clk In PHY to TEMAC receive clock.
gmii_tx_clk In PHY to TEMAC TX input clock in 10 and 100 Mbps modes.