The pattern generator can be enabled/disabled using a DIP
switch. When enabled, the data from the RX FIFO is flushed and the
axi_pat_gen module drives the address_swap module
inputs.
Using parameters, the pattern generator allows user modification of these items:
- Destination address
- Source address
- Minimum frame size
- Maximum frame size
When enabled using a dedicated input mapped to a DIP switch on the board, the pattern generator begins with the minimum frame size and, after each frame is sent, increments the frame size until the maximum value is reached. The cycle then repeats beginning with the minimum frame size.
The destination and source addresses are as provided by HDL parameters. The Type/Length field is dependent upon the frame size and the frame data consists of the count value.