When the core is configured to use GMII or
RGMII interface on UltraScale or UltraScale+ devices, you need to set
the REFCLK_FREQUENCY attribute of all the IDELAY and
ODELAY primitives used by the core to the frequency of the clock driving the ref_clk port. This can be done through XDC constraints.
For more information, refer to the example design in Vivado.
set_property
REFCLK_FREQUENCY <ref_clk> [get_cells -hier -filter {NAME =~
*<cell_name>}]
Note: The AXI Ethernet Subsystem is a
hierarchical IP, and consequently does not have a core XDC. The subcore XDC
constraints are automatically applied. It is recommended to check the AXI
Ethernet IP example design XDC and apply the constraints (if any) to the top XDC
for board and part based subsystem designs.