Bits | Name | Access | Reset Value | Description |
---|---|---|---|---|
31 | RST | R/W | 0 |
Reset: When this bit is 1, the receiver is reset. The bit
automatically resets to 0. The reset also sets all of the receiver configuration
registers to their default values. Resetting the receiver without resetting the
subsystem can place the subsystem in an unknown state.
|
30 | JUM 1 | R/W | 0 |
Jumbo Frame Enable: When this bit is 1 the receiver accepts frames
over the maximum length specified in IEEE Std 802.3-2002 specification.
|
29 | FCS | R/W | 0 |
In-Band FCS Enable: When this bit is 1, the receiver provides the
FCS field with the rest of the frame data. When this bit is 0 the FCS field is
stripped from the receive frame data. In either case the FCS field is verified.
|
28 | RX 2 | R/W | 1 |
Receive Enable: When this bit is 1, the receiver logic is enabled to
operate. When this bit is 0, the receiver ignores activity on the receive
interface.
|
27 | VLAN | R/W | 0 |
VLAN Frame Enable: When this bit is 1, the receiver accepts VLAN
tagged frames. The maximum payload length increases by four bytes.
|
26 | HD | R/W | 0 |
Half-Duplex Mode: When this bit is 1, the receive operates in
half-duplex mode. When this bit is 0, the receiver operates in full-duplex mode.
Only full-duplex is supported so this bit should always be set to
0.
|
25 | LT_DIS | R/W | 0 |
Length/Type Field Valid Check Disable: When this bit is 1, it
disables the Length/Type field check on the receive frame.
|
24 | CL_DIS | R/W | 0x0 | Control Frame Length Check Disable: When this bit is 1, control frames larger than the minimum frame length can be accepted |
23 | Reserved | Reserved . | ||
22 | R/W | 0 |
Inband 1588 Timestamp Enable. When 0, Timestamp is only provided out-of-band. When 1, the Timestamp is provided in-Line in addition to out-of-band. When the TEMAC does not include 1588 functionality, this bit is ignored because no timestamp is present. |
|
21:16 | Reserved | RO | 0x0 | Reserved: These bits are reserved for future use and always return zero. |
15:0 | PauseAddr | R/W | 0xFFFF |
Pause Frame Ethernet MAC Address (47:32): This address is used to
match the destination address of any received flow control frames. It is also used as
the source address for any transmitted flow control frames. This address is ordered so that the first byte transmitted/ received is the lowest position byte in the register. For example, an Ethernet MAC address of AA-BB-CC-DD-EE-FF would be stored in the PauseAddr(47:0) as 0xFFEEDDCCBBAA. |
|
The TEMAC Transmit Configuration (TC) register is shown in the following figure. This register can be written at any time but the transmitter logic only applies the configuration changes during Inter-Frame gaps. The exception to this is the Reset bit, which is effective immediately.
The following table shows the TEMAC Transmit Configuration register bit definitions.
Bits | Name | Access | Reset Value | Description |
---|---|---|---|---|
31 | RST | R/W | 0 |
Reset: When this bit is 1, the transmitter is reset. The bit
automatically resets to 0. The reset also sets all of the transmitter configuration
registers to their default values. Resetting the transmitter without resetting the
subsystem can place the subsystem in an unknown state.
|
30 | JUM 1 | R/W | 0 |
Jumbo Frame Enable: When this bit is 1 the transmitter sends frames
over the maximum length specified in IEEE Std 802.3-2002 specification.
|
29 | FCS | R/W | 0 |
In-Band FCS Enable: When this bit is 1, the transmitter accepts the
FCS field with the rest of the frame data. When this bit is 0 the FCS field is
calculated and supplied by the transmitter. In either case the FCS field is
verified.
|
28 | TX 2 | R/W | 1 |
Transmit Enable: When this bit is 1, the transmit logic is enabled
to operate.
|
27 | VLAN | R/W | 0 |
VLAN Frame Enable: When this bit is 1, the transmitter allows
transmission of VLAN tagged frames.
|
26 | HD | R/W | 0 |
Half-Duplex Mode: When this bit is 1, the transmitter operates in
half-duplex mode. When this bit is 0, the transmitter operates in full-duplex mode.
Only full-duplex is supported so this bit should always be set to
0 .
|
25 | IFG | R/W | 0 |
Inter Frame Gap Adjustment Enable: When this bit is 1, the
transmitter uses the value of the IFGP register (Transmit Inter Frame Gap Adjustment Register) to
extend the transmit Inter Frame Gap beyond the minimum of 12 idle cycles (96-bit times
on the Ethernet Interface).
|
24:23 | RO | Reserved | ||
22 | RW |
Inband 1588 Command Field Enable. When 0, the Command Field is provided out-of-band. When 1, the Command Field is provided in-Line. When the TEMAC does not include 1588 functionality, this bit is ignored because no Command Field is present. |
||
21:0 | RO | Reserved: These bits are reserved for future use and always return zero. | ||
|