FINMAX_XPLL
|
Maximum input clock frequency
2
|
1150 |
1150 |
1070 |
984 |
800 |
680 |
MHz |
FINMIN_XPLL
|
Minimum input clock frequency |
100 |
100 |
100 |
100 |
100 |
100 |
MHz |
FINJITTER_XPLL
|
Maximum input clock jitter
3
|
< 20% of clock input period or
1 ns Max |
FINDUTY_XPLL
|
Allowable input duty cycle: 100–399 MHz |
35–65 |
% |
Allowable input duty cycle: 400–499 MHz |
40–60 |
% |
Allowable input duty cycle: >500 MHz |
45–55 |
% |
FPSCLKMAX_XPLL
|
Maximum dynamic phase shift clock frequency |
300 |
300 |
300 |
300 |
300 |
300 |
MHz |
FPSCLKMIN_XPLL
|
Minimum dynamic phase shift clock frequency |
0.01 |
0.01 |
0.01 |
0.01 |
0.01 |
0.01 |
MHz |
FVCOMAX_XPLL
|
Maximum XPLL VCO frequency |
4320 |
4320 |
4320 |
4320 |
4320 |
4320 |
MHz |
FVCOMIN_XPLL
|
Minimum XPLL VCO frequency |
2160 |
2160 |
2160 |
2160 |
2160 |
2160 |
MHz |
FBANDWIDTH_XPLL
|
XPLL bandwidth at typical
4
|
14.00 |
14.00 |
14.00 |
14.00 |
14.00 |
14.00 |
MHz |
TSTATPHAOFFSET_XPLL
|
Static phase offset of the XPLL outputs
5
|
0.12 |
0.12 |
0.12 |
0.12 |
0.12 |
0.12 |
ns |
TOUTJITTER_XPLL
|
XPLL output jitter |
Note 6
|
TOUTDUTY_XPLL
|
XPLL CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3 duty-cycle
precision
7
|
0.125 |
0.15 |
0.15 |
0.15 |
0.15 |
0.15 |
ns |
TLOCKMAX_XPLL
|
XPLL maximum lock time (in non-deskew mode) |
100 |
100 |
100 |
100 |
100 |
100 |
µs |
TLOCKDESKEWMAX_XPLL
|
XPLL maximum lock time in deskew mode |
Note 8
|
FOUTMAX_XPLL
|
XPLL maximum output frequency at CLKOUT0, CLKOUT1, CLKOUT2,
CLKOUT3
2,9
|
1150 |
1150 |
1070 |
984 |
800 |
680 |
MHz |
XPLL maximum output frequency at CLKOUTPHY |
4266 |
4266 |
3933 |
3733 |
3933 |
3733 |
MHz |
FOUTMIN_XPLL
|
XPLL minimum output frequency at CLKOUT0, CLKOUT1, CLKOUT2,
CLKOUT3 |
16.875 |
16.875 |
16.875 |
16.875 |
16.875 |
16.875 |
MHz |
XPLL minimum output frequency at CLKOUTPHY |
200 |
200 |
200 |
200 |
200 |
200 |
MHz |
TPWRDWNMINPULSE_XPLL
|
Minimum power-down pulse width |
5.00 |
5.00 |
5.00 |
5.00 |
5.00 |
5.00 |
ns |
FPFDMAX_XPLL
|
Maximum frequency at the phase frequency detector with
bandwidth set to High optimized |
667.5 |
667.5 |
667.5 |
667.5 |
667.5 |
667.5 |
MHz |
FPFDMIN_XPLL
|
Minimum frequency at the phase frequency detector |
100 |
100 |
100 |
100 |
100 |
100 |
MHz |
TDESKEWTAPEDELAY_XPLL
|
Nominal tap-delay of the programmable delay in the PD based
deskew scheme |
Note 10
|
- The XPLL is powered by the VCC_IO supply that operates at 0.80V in low (L) voltage
operation, see
Table 1.
- The maximum input clock frequency and
output clock frequency at CLKOUT0, CLKOUT1, CLKOUT2, and CLKOUT3 are limited by
the global clock buffers. See
Table 1.
- CLKIN jitter also applies to CLKIN_DESKEW
and CLKFB_DESKEW in digital compensation. CLKFBIN applies only to analog
compensation. This parameter is in regards to the functionality of the XPLL. Input
jitter above ~1 MHz is reduced by the filtering properties of the XPLL. The
magnitude of the reduction is found in the Vivado timing report.
- The XPLL does not filter typical
spread-spectrum input clocks because they are usually far below the loop filter
frequencies.
- The static offset is measured
between any XPLL outputs with identical phase.
- Values for this parameter are available
in the Vivado timing summary as part of the
clock uncertainty equation.
- Includes global clock buffer.
- The maximum lock time in deskew mode is
given by the following formula: Lock time in deskew mode in μs = (208 x
(VCO_frequency in MHz) / (CLKIN_DESKEW_frequency in MHz)2 + 100.
- XPLL CLKOUTs FMAX is increased in the -1L/-2L speed grade when it directly drives the
memory controller at a 1/4 x DDR bit rate. Refer to the DDR bit rate in Table 1.
- The value for this parameter is
included in compensation delay calculations.
|