Revision History - DS959

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
Document ID
DS959
Release Date
2024-06-25
Revision
1.7 English

The following table shows the revision history for this document.

Section Revision Summary
6/25/2024 Version 1.7
General updates

Updated the Table 1 to include:

  • Production release of the XCVP1902 devices with speed grades -3HSE, -2MSE, -2MLE, -2LSE, -2LLI, -1MSE, and -1LSE using the Vivado Design Suite 2024.1 v2.01.
  • Production release of the XQVP1052 devices with speed grades -2MSI, -1MSM, -1MSI, and -1LSI using the Vivado Design Suite 2024.1.1 v2.02.
  • Production release of the XQVP1702 devices with speed grades -2MSI, -1MSI, and -1LSI using the Vivado Design Suite 2024.1.1 v2.0.8.
  • Production release of the XQVP2502 devices with speed grades -2MSI, -1MSI, and -1LSI using the Vivado Design Suite 2024.1.1 v2.0.2.

This includes updates to the following tables:
Available Speed Grades and Operating Voltages Revised -2LLI standard speed grade for VCCINT = 0.70V with clarifications in Note 5.
Production Silicon and Software Status Updated XCVP1102 and XCVP1052 with Note 3.
Processing System Performance Characteristics Updated notes in Table 1 and Table 2.
Clocks and Reset Added the FCPM5_TOPSW_CLK to Table 5.
PMC JTAG and SelectMAP Updated Table 1 to include XCVP1902 devices.
Programmable Logic Performance Characteristics Added XCVC1902 performance specifications to Table 3.
Programmable Logic Integrated Block for PCIe Inserted Note 1.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) Inserted Notes 1, 1, and 1 to point to the product guides for each application.
4/30/2024 Version 1.6
General updates Updated the Table 1 to include:
  • Production release of the XCVP1002 and XCVP1052 devices with speed grades -2HSI, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI using the Vivado Design Suite 2023.2.2 v2.01.
  • Production release of the XCVP2502 and VCVP2802 devices with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.2.2 v2.01.

This includes updates to the following tables:
Absolute Maximum Ratings Added VCCINT_GT specification.
Recommended Operating Conditions Updated VGTYP_AVCC and VGTYM_AVCC with voltages based upon temperature ranges (E, I, Q, or M).
Available Speed Grades and Operating Voltages Updated Note 5.
Power Supply Requirements Added reference links.
DDR4 and LPDDR4/4X Memory Interface Controller Updated Note 5.
Table 2 Revised VIDIFF maximum.
Table 2 Revised VIDIFF maximum.
GTY and GTYP Transceiver Reference Clock Oscillator Selection Phase Noise Mask Interchanged symbols LCPLL and RINGPLL.
2/29/2024 Version 1.5
General updates Updated the Table 1 to include:
  • Production release of the XCVP1002 and XCVP1052 devices with speed grades -2LSE, -2LLE, -2LLI, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.2.1 v2.00.
  • Production release of the XCVP2502 and VCVP2802 devices with speed grades -3HSE, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI using the Vivado Design Suite 2023.2.1 v2.00.

This includes updates to the following tables:
Absolute Maximum Ratings Revised the transceiver REFCLK_AC maximum input voltage from 1.200V to 1.350V.
Block RAM Switching Characteristics Changed TRCKO_DO -2LLI values.

Changed TRCKO_DO_REG values for -2M, -2L, and -2LLI.
Device Pin-to-Pin Output Parameter Guidelines The XQXP1702 speed grade designation is in evaluation.
Package Parameter Guidelines Added the SBVJ1369 package to the VP1052.
DDR4 and LPDDR4/4X Memory Interface Controller Removed the LPDDR4/4X pin efficient component interface limitation.
Table 2 Removed the rows, columns, and interface tiles connected to PL columns. See Versal Architecture and Product Data Sheet: Overview (DS950) for the most up to date information.
Table 2 Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV.
GTM Transceiver Performance Added Note 1.
GTM Transceiver PLL/Lock Time Adaptation Update the TDLOCK values for GTM PAM4.
GTM Transceiver User Clock Switching Characteristics Updated tables to contain -2H values for some devices.
Table 2 Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated tables to contain -2H values for some devices.
11/09/2023 Version 1.4
General updates Updated the Table 1 to include:
  • Production release of the XCVP1552 device with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.2 v2.01.
  • Production release of the XCVP1552 device with speed grades -3HSE, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI using the Vivado Design Suite 2023.1.2 v2.00.
  • Production release of the XQVP1202 device with speed grades -2MSI, -1MSM, -1MSI, and -1LSI using the Vivado Design Suite 2023.2 v2.04.
  • Production release of the XQVP1402 device with speed grades -2MSI, -1MSM, -1MSI, and -1LSI using the Vivado Design Suite 2023.2 v2.02.
  • Production release of the XQVP1502 device with speed grades -2MSI, -1MSI, and -1LSI using the Vivado Design Suite 2023.2 v2.06.

This includes updates to the following tables:
Absolute Maximum Ratings Updated the VCCO specs for XPIO and HDIO.
Recommended Operating Conditions Updated Note 9 with information on the PSIO and added specific conditions for the VP1202 device.
Updated the VCCO specs for XPIO and HDIO.
Updated Note 10.
Available Speed Grades and Operating Voltages Updated Note 4.
DC Characteristics Over Recommended Operating Conditions Updated Note 3 to clarify how to design with specific devices.
PMC JTAG and SelectMAP Updated FCK with values for the XCVP1902 device.
DDR4 and LPDDR4/4X Memory Interface Controller Updated the LPDDR4/LPDDR4X rows and added Note 6.
GTM Transceiver Reference Clock Switching Characteristics Added Note 1.
GTM Transceiver Digital Monitor Clock Added table.
GTY and GTYP Transceiver Reference Clock Switching Characteristics Added Note 1.
GTY and GTYP Transceiver Digital Monitor Clock Added table.
GTY and GTYP Transceiver Electrical Compliance Added the PCI Express 5.0 protocol for GTYP transceivers.
8/16/2023 Version 1.3
General updates Updated the Table 1 to include:
  • Production release of the XCVP1102 and XCVP1402 devices with speed grades -3HSE, -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, -1MLI using the Vivado Design Suite 2023.1.1 v2.01.
  • Production release of the XCVP1502, XCVP1702, XCVP1802 devices with speed grade -3HSE using the Vivado Design Suite 2023.1.1 v2.04.
  • Production release of the XCVP1102 and XCVP1402 devices with speed grades -2LSE, -2LLE, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.1 v2.00.
  • Production release of the XCVP1502, XCVP1702, XCVP1802 devices with speed grades -2MSE, -2MLE, -2MSI, -2MLI, -2LSE, -2LLE, -1MSE, -1MSI, -1MLI, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2023.1 v2.01.
Added the XCVP1902 device where applicable.
Recommended Operating Conditions Updated VCC_PMC with specifications for -2LSE, 2LLE, -2MSE, -2MLE, -2MSI, and -2MLI devices.
DC Characteristics Over Recommended Operating Conditions Added IL specifications.
Multiport RAM Switching Characteristics Added multiport RAM specifications.
Clock Buffers and Networks Updated FMAX specifications in Table 1 for VP1102 and VP1402.
Production Silicon and Software Status Corrected the XCVP1202 production release to v2.01 in Vivado Design Suite 2022.2.2.
Table 4 Added Notes 1, 2, and 3.
Table 5 Added Notes 2, 4, 6, 8, 10, and 12.
PS Gigabit Ethernet MAC Controller Interface Added Note 2 to FGEMTSUREFCLK.
Device Pin-to-Pin Output Parameter Guidelines Added and updated values. Also, to clarify specifications by speed grade and temperature, added -2LLI column.
Device Pin-to-Pin Input Parameter Guidelines Added and updated values. Also, to clarify specifications by speed grade and temperature, added -2LLI column.
Package Parameter Guidelines Added more values, updated device package combinations.
AI Engine Switching Characteristics Added the tables for the XCVP2502 and XCVP2802 devices.
GTM Transceiver DC Input and Output Levels Add VCMOUTDC to Table 1.
GTY and GTYP Transceiver DC Input and Output Levels Removed the row for VCMOUTDC when remote RX is terminated to GND and added Note 2. Updated Note 3.
GTY and GTYP Transceiver Electrical Compliance Updated to add the PCIe Gen 4 and Gen 5 protocols.
3/28/2023 Version 1.2
General updates Updated the Table 1 including:
  • Production release of the XCVP1202 and with speed grades -3HSE, -2LSE, -2LLE, -1MSE, -1MSI, -1MLI, -1LSE, -1LSI, and -1LLI using the Vivado Design Suite 2022.2.2 v2.01.
  • Production release of the VP1502, XC1702, and XC1802 devices in the -2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, and -1MLI speed grades using the Vivado Design Suite 2022.2.2 v2.00.
Absolute Maximum Ratings Revised the IDCIN_GTM_AVTT and IDCIN_GTM_GND values from 12 mA to 16 mA.
Recommended Operating Conditions Updated VCCINT with values for -2LLI devices and added Note 7.
Available Speed Grades and Operating Voltages Updated -2LLI device code and added Note 5.
Updated VCC_CPM5 values because devices with CPM5 do not support the -2HSI or -2LLI speed grades.
Updated Notes 1, 2, and 3.
DC Characteristics Over Recommended Operating Conditions Added Note 3 to the CIN and IRPU values to be used for devices with super-logic regions (SLRs).
AC Switching Characteristics Updated the speed specification version to 2022.2.2.
Speed Grade Designations Moved the XCVP1102, XCVP1402, XCVP1552, VP2502, and VP2802 to engineering sample.
Device Identification Revised the XCVP1102, XCVP1202, XCVP1402, XCVP1502, XCVP1552, XCVP1702, XCVP1802, XCVP2502, and VP2802 IDCODEs.
Block RAM Switching Characteristics Updated table to delineate the clock-to-out delay values between the -2LLI, -2LSE, and -2LLE static screen and temperature grades.
Clock Buffers and Networks Updated Table 1 to include FMAX specifications by device.
Device Pin-to-Pin Output Parameter Guidelines Added VP1102, VP1402, VP2502, and VP2802 values and updated the VP1502, VP1702 and VP1802 values.
Device Pin-to-Pin Input Parameter Guidelines Added VP1102, VP1402, VP2502, and VP2802 values and updated the VP1202, VP1502, VP1702 and VP1802 values.
Package Parameter Guidelines Added values for the XCVP1102-VSVA2785, VP1402-(VSVD2192, VSVA2785, VSVA3340), XCVP1552-VSVA3340, XCVP1702-VSVA5601, XCVP1802-VSVA5601, XCVP2502-VSVB3340, and XCVP2802-VSVA5601.
GTM Transceiver DC Input and Output Levels Updated the TOSKEW maximum value an added Note 2.
Table 1 Added the PAM4, 58 Gb/s condition and Note 1.
GTM Transceiver PLL/Lock Time Adaptation Updated conditions for TLOCK.
Table 2 Added the PAM4, 58 Gb/s condition and Note 1.
Integrated Interface Block for Interlaken Added Note 3.
12/05/2022 Version 1.1
General updates Updated the following tables for production release of some of the speed grade/operating voltages of the VP1202 -2M (VCCINT = 0.80) in Vivado Design Suite v2022.2 v2.00.
Added overdrive specifications (where applicable) to Table 1 and Table 2.
Recommended Operating Conditions Added Note 7 for the -2LLI VCCINT (Low).
Available Speed Grades and Operating Voltages Added Note 5.
DC Characteristics Over Recommended Operating Conditions Updated the ICC_BATT conditions and values.
PMC JTAG and SelectMAP Updated Note 1 in Table 1 to include all transceivers when using AC-JTAG.
PMC Quad-SPI Controller Interface Updated the FQSPI_REFCLK maximum for Quad-SPI device clock frequency operating at ≤37.5 MHz (Loopback disabled) from 150 MHz to 300 MHz.
PMC SD/SDIO Controller Interface Added TSDDCK and TSDCKD to the table and revised the minimum value for TSDSDR12DCK to 10.0 ns.
PMC eMMC Controller Interface Added TEMMCDCK and TEMMCCKD.
Package Parameter Guidelines Removed VSVC2197 package from the list of packages for the VP1202.
Device Identification Revised the VP1202 IDCODE for production.
GTM Transceiver DC Input and Output Levels Updated the DVPPIN PAM4 maximum specification in Table 1. Also revised the VCMOUTDC conditions and equations. Added Table 3.
GTM Transceiver Performance Revised the GTM transceiver PAM4 maximum line rate.
GTM Transceiver PLL/Lock Time Adaptation Updated conditions for TLOCK.
GTM Transceiver Transmitter and Receiver Switching Characteristics Removed the PAM4 82.5 Gb/s sinusoidal jitter condition.
Table 2 Updated RXPPMTOL conditions and Note 2, and added Note 5.
GTM Transceiver Electrical Compliance Updated table with 106.25 Gb/s protocol information.
Table 1 Revised table and added Notes 2 and 3.
GTY and GTYP Transceiver DC Input and Output Levels Revised VCMOUTDC and VCMOUTAC equations. Updated values in Table 3.
GTY and GTYP Transceiver Performance Revised the GTYP maximum line rate.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated FTXIN and FRXIN.
Integrated Block for DCMAC Updated the -3/-2 (0.88V), -2 (0.80V), and -2 (0.70V) AXI4-Stream interface clock values.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) Added the -1 (0.70V) overdrive values for some of the frequencies in this topic.
5/02/2022 Version 1.0
Initial release. N/A