FINMAX_DPLL
|
Maximum input clock frequency
2
|
1150 |
1150 |
1070 |
984 |
800 |
680 |
MHz |
FINMIN
_DPLL
|
Minimum input clock frequency |
50 |
50 |
50 |
50 |
50 |
50 |
MHz |
FINJITTER
_DPLL
|
Maximum input clock jitter
3
|
< 20% of clock input period or
1 ns Max |
FINDUTY_DPLL
|
Input duty cycle range: 50–399 MHz |
35–65 |
% |
Input duty cycle range: 400–499 MHz |
40–60 |
% |
Input duty cycle range: >500 MHz |
45–55 |
% |
FPSCLKMAX_DPLL
|
Maximum dynamic phase shift clock frequency |
550 |
500 |
500 |
450 |
500 |
450 |
MHz |
FPSCLKMIN_DPLL
|
Minimum dynamic phase shift clock frequency |
0.01 |
0.01 |
0.01 |
0.01 |
0.01 |
0.01 |
MHz |
FDCOMAX_DPLL
|
Maximum DPLL DCO frequency |
4000 |
4000 |
4000 |
4000 |
4000 |
4000 |
MHz |
FDCOMIN_DPLL
|
Minimum DPLL DCO frequency |
2000 |
2000 |
2000 |
2000 |
2000 |
2000 |
MHz |
FBANDWIDTH_DPLL
|
DPLL bandwidth at typical
4
|
1.00 |
1.00 |
1.00 |
1.00 |
1.00 |
1.00 |
MHz |
TSTATPHAOFFSET_DPLL
|
Static phase offset of the DPLL outputs
5
|
0.12 |
0.12 |
0.12 |
0.12 |
0.12 |
0.12 |
ns |
TOUTJITTER_DPLL
|
DPLL output jitter |
Note 6
|
TOUTDUTY_DPLL
|
DPLL output clock duty cycle precision
7
|
0.165 |
0.20 |
0.20 |
0.20 |
0.20 |
0.20 |
ns |
TLOCKMAX_DPLL
|
DPLL maximum lock time (non-deskew mode) |
Note 8
|
TLOCKDESKEWMAX_DPLL
|
DPLL maximum lock time in deskew mode
|
Note 9
|
FOUTMAX_DPLL
|
DPLL maximum output clock frequency
2
|
1150 |
1150 |
1070 |
984 |
800 |
680 |
MHz |
FOUTMIN_DPLL
|
DPLL minimum output clock frequency |
5 |
5 |
5 |
5 |
5 |
5 |
MHz |
TPWRDWNMINPULSE_DPLL
|
Minimum power-down pulse width |
5.00 |
5.00 |
5.00 |
5.00 |
5.00 |
5.00 |
ns |
FTDCMAX_DPLL
|
Maximum frequency at the time to digital converter |
200 |
200 |
200 |
200 |
200 |
200 |
MHz |
FTDCMIN_DPLL
|
Minimum frequency at the time to digital converter |
50 |
50 |
50 |
50 |
50 |
50 |
MHz |
TDESKEWTAPDELAY_DPLL
|
Nominal tap-delay of the programmable delay in the PD based
deskew scheme
|
Note 10
|
- The DPLLs are powered by the
VCC_RAM supply, except for the DPLLs at HDIO banks
are powered by the VCCINT supply. The VCC_RAM supply operates at 0.80V in low (L) voltage
operation, see
Table 1.
- The maximum input and output
clock frequencies are limited by the global clock buffers. See
Table 1.
- CLKIN jitter also applies to CLKIN_DESKEW
and CLKFB_DESKEW in digital compensation. CLKFBIN applies only to analog
compensation. This parameter is in regards to the functionality of the DPLL. Input
jitter above ~1 MHz is reduced by the filtering properties of the DPLL. The
magnitude of the reduction is found in the Vivado timing report.
- The DPLL does not filter typical
spread-spectrum input clocks because they are usually far below the bandwidth
filter frequencies.
- The static offset is measured
between any DPLL outputs with identical phase.
- Values for this parameter are available
in the Vivado timing summary as part of the
clock uncertainty equation.
- Includes global clock buffer.
- The maximum lock time in
non-deskew mode is given by the given formula: Lock time in non-deskew mode in ms
= 153.6 × DIVCLK_DIVIDE / (CLKIN_FREQUENCY in MHz).
- The maximum lock time in deskew mode is
given by the following formula: Lock time in deskew mode in ms = (0.208 x
(VCO_frequency in MHz) / (CLKIN_DESKEW_frequency in MHz)2) + (maximum lock time in non-deskew mode in ms from Note 8).
- The value for this parameter is
included in compensation delay calculations.
|